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    Cell layouts
    1.
    发明授权
    Cell layouts 有权

    公开(公告)号：US12288782B2

    公开(公告)日：2025-04-29

    申请号：US17679655

    申请日：2022-02-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Juhan Kim ,  Sangmoon J. Kim ,  Mahbub Rashed ,  Navneet K. Jain

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/417

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

    STRUCTURE AND METHOD TO GROUND REFERENCE VOLTAGE GENERATOR
    2.
    发明公开
    STRUCTURE AND METHOD TO GROUND REFERENCE VOLTAGE GENERATOR 审中-公开

    公开(公告)号：US20240274161A1

    公开(公告)日：2024-08-15

    申请号：US18166544

    申请日：2023-02-09

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Dzung T. Tran ,  Navneet K. Jain

    IPC: G11C5/14 ,  G01R19/165

    CPC classification number: G11C5/147 ,  G01R19/16519

    Abstract: Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

    INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING MIXED TRACK HEIGHT
    3.
    发明公开
    INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING MIXED TRACK HEIGHT 审中-公开

    公开(公告)号：US20240222356A1

    公开(公告)日：2024-07-04

    申请号：US18149279

    申请日：2023-01-03

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

    IPC: H01L27/02

    CPC classification number: H01L27/0207

    Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

    Structure including a cross-bar router and method
    4.
    发明授权
    Structure including a cross-bar router and method 有权

    公开(公告)号：US12027226B2

    公开(公告)日：2024-07-02

    申请号：US17810018

    申请日：2022-06-30

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Navneet K. Jain ,  Sven Beyer

    IPC: G11C16/04 ,  G11C5/06 ,  G11C11/22 ,  G11C13/00

    CPC classification number: G11C5/063 ,  G11C11/22 ,  G11C13/0028 ,  G11C13/0069

    Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

    DEEP NWELL CONTACT STRUCTURES
    6.
    发明公开
    DEEP NWELL CONTACT STRUCTURES 审中-公开

    公开(公告)号：US20230282707A1

    公开(公告)日：2023-09-07

    申请号：US17687941

    申请日：2022-03-07

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet K. Jain ,  Mahbub Rashed

    IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78

    CPC classification number: H01L29/1087 ,  H01L27/1203 ,  H01L29/7838

    Abstract: Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.

    AREA-EFFICIENT FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR STRUCTURE WITH MIXED THRESHOLD VOLTAGE TRANSISTORS
    7.
    发明申请
    AREA-EFFICIENT FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR STRUCTURE WITH MIXED THRESHOLD VOLTAGE TRANSISTORS 有权

    公开(公告)号：US20250120175A1

    公开(公告)日：2025-04-10

    申请号：US18482107

    申请日：2023-10-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet K. Jain ,  Juhan Kim ,  Mahbub Rashed

    IPC: H01L27/118 ,  H03K19/20

    Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

    FIN-TYPE FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASABLE SUPPLEMENTARY GATE AND METHOD
    8.
    发明申请
    FIN-TYPE FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASABLE SUPPLEMENTARY GATE AND METHOD 有权

    公开(公告)号：US20250031439A1

    公开(公告)日：2025-01-23

    申请号：US18354114

    申请日：2023-07-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hong Yu ,  Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette

    IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234

    Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.

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