公开(公告)号：US07468534B2

公开(公告)日：2008-12-23

申请号：US11216417

申请日：2005-08-30

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27/108

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US07285811B2

公开(公告)日：2007-10-23

申请号：US11513244

申请日：2006-08-31

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L29/76 ,  H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract translation: 本发明提供一种在制造期间使电短路发生最小化的MRAM电池。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元的厚度的厚度。 图案化和蚀刻第一介电层以在单元形状的第一导体上形成开口。 包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

公开(公告)号：US07034353B2

公开(公告)日：2006-04-25

申请号：US09965240

申请日：2001-09-26

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

公开(公告)号：US06673675B2

公开(公告)日：2004-01-06

申请号：US10119952

申请日：2002-04-11

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L21336

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 然后，将第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元厚度的厚度。 然后对第一介电层进行图案化和蚀刻，以在单元形状的第一导体上形成开口。 然后，包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

公开(公告)号：US06833084B2

公开(公告)日：2004-12-21

申请号：US09285773

申请日：1999-04-05

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。

公开(公告)号：US06794704B2

公开(公告)日：2004-09-21

申请号：US10050390

申请日：2002-01-16

Applicant: Donald L. Yates ,  Garry A. Mercaldi ,  James J. Hofmann

Inventor： Donald L. Yates ,  Garry A. Mercaldi ,  James J. Hofmann

IPC: H01L27108

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Lower electrodes of capacitors composed of a texturizing underlayer and a conductive material overlayer are provided. The lower electrodes have an upper roughened surface. In one embodiment, the texturizing layer is composed of porous or relief nanostructures comprising a polymeric material, for example, silicon oxycarbide. In another embodiment, the texturizing underlayer is in the form of surface dislocations composed of annealed first and second conductive metal layers, and the conductive metal overlayer is agglomerated onto the surface dislocations as nanostructures in the form of island clusters.

Abstract translation: 提供了由纹理化底层和导电材料覆盖层组成的电容器的下部电极。 下部电极具有上部粗糙表面。 在一个实施方案中，组织化层由包含聚合物材料的多孔或释放纳米结构组成，例如碳氧化硅。 在另一个实施方案中，所述织构化底层是由退火的第一和第二导电金属层组成的表面位错的形式，并且所述导电金属覆层作为岛簇形式的纳米结构聚集到所述表面位错上。

公开(公告)号：US06682970B1

公开(公告)日：2004-01-27

申请号：US09692897

申请日：2000-10-19

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L218242

CPC classification number: H01L27/11502 ,  G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/84

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier material.

Abstract translation: 半导体结构包括具有第一和第二相对侧的电介质层。 导电层与电介质层的第一侧相邻并且耦合到第一端子，并且导电阻挡层与电介质层的第二侧相邻并耦合到第二端子。 导电阻挡层可以由氮化钨，氮化钨，氮化钛或其它阻挡材料形成。

公开(公告)号：US06521945B2

公开(公告)日：2003-02-18

申请号：US10060532

申请日：2002-01-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L29792

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US06251693B1

公开(公告)日：2001-06-26

申请号：US09126983

申请日：1998-07-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L2166

CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly-distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon-containing material.

Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在无规分布的介电层特征上而不是在其它基底区域上。 随后检查衬底以进行选择性沉积的含硅材料。

公开(公告)号：US6150706A

公开(公告)日：2000-11-21

申请号：US32182

申请日：1998-02-27

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: G11C11/404 ,  G11C17/16 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/00

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.