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公开(公告)号：US09954165B2
公开(公告)日：2018-04-24
申请号：US15500085
申请日：2015-01-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Hans S. Cho , Yoocharn Jeon
CPC classification number: H01L45/124 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1616 , H01L45/1675
Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.
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公开(公告)号：US09721656B2
公开(公告)日：2017-08-01
申请号：US15113908
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gregg B. Lesartre , Gary Gibson , Erik Ordentlich , Yoocharn Jeon
CPC classification number: G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
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公开(公告)号：US09558820B2
公开(公告)日：2017-01-31
申请号：US15031106
申请日：2013-10-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Frederick Perner , Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/003 , G11C13/0069 , G11C2213/15 , G11C2213/72 , G11C2213/73
Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.
Abstract translation: 一种方法包括在包括易失性选择器开关和非易失性开关的组合存储器件中施加电压突起，其中电压凸起将易失性选择器开关的状态从高电阻改变为低电阻，但不改变 非易失性开关。 读取电压低于组合存储器件上的电压突起，以读取非易失性开关的状态。
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公开(公告)号：US09972387B2
公开(公告)日：2018-05-15
申请号：US15325040
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Martin Foltin , Yoocharn Jeon , Brent Buchanan , Erik Ordentlich , Naveen Muralimanohar , James S. Ignowski , Jacquelyn M. Ingemi
CPC classification number: G11C13/004 , G11C7/06 , G11C13/0038 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2207/068
Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.
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公开(公告)号：US09911915B2
公开(公告)日：2018-03-06
申请号：US15318089
申请日：2014-07-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Yoocharn Jeon , Hans S. Cho
CPC classification number: H01L45/146 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/165
Abstract: A multiphase selector includes a first electrode, a switching layer coupled to the first electrode, a capping layer coupled to the switching layer, and a second electrode coupled to the capping layer. The switching layer may include a matrix having a first, relatively insulating phase of a transition metal oxide; a second, relatively conducting phase of the transition metal oxide dispersed in the matrix; and a catalyst, located within the matrix, to interact with the first phase of the transition metal oxide to selectively form and position the second phase of the transition metal oxide within the matrix.
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Patent Agency Ranking
公开(公告)号：US09761309B2
公开(公告)日：2017-09-12
申请号：US15114760
申请日：2014-02-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C2013/0054 , G11C2213/70 , G11C2213/77
Abstract: A method and a circuit for reading resistive states of memory elements within crossbar arrays includes a first crossbar array having first sets of row firms and column lines, with memory elements disposed at the intersections between the row lines and the column lines, a second crossbar array having second sets of row lines and column lines, with memory elements disposed at the intersections between the row lines and the column lines, and a comparator having a first input connected to the first crossbar array and a second input connected to the second crossbar array, wherein the first input is configured to receive a sense voltage from as select column in the first crossbar array and the second input is configured to receive a reference voltage from a corresponding select column in the second crossbar array.
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公开(公告)号：US20170213591A1
公开(公告)日：2017-07-27
申请号：US15329776
申请日：2014-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/77
Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.
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公开(公告)号：US20160267970A1
公开(公告)日：2016-09-15
申请号：US15031106
申请日：2013-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Frederick Perner , Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/003 , G11C13/0069 , G11C2213/15 , G11C2213/72 , G11C2213/73
Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.
Abstract translation: 一种方法包括在包括易失性选择器开关和非易失性开关的组合存储器件中施加电压突起，其中电压凸起将易失性选择器开关的状态从高电阻改变为低电阻，但不改变 非易失性开关。 读取电压低于组合存储器件上的电压突起，以读取非易失性开关的状态。
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公开(公告)号：US10460800B2
公开(公告)日：2019-10-29
申请号：US15748667
申请日：2015-07-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B Lesartre , Martin Foltin , Yoocharn Jeon
IPC: G11C11/00 , G11C13/00 , G11C7/06 , G11C7/10 , G11C11/4074
Abstract: A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
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公开(公告)号：US10049732B2
公开(公告)日：2018-08-14
申请号：US15500052
申请日：2015-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
Abstract: In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias voltage causes a bias current to pass through a target memristor along the target row line. The bias voltage is increased by a predetermined amount to a state voltage. A state current flowing through the target memristor is determined. The state current is based on the state voltage. A state of the target memristor is determined based on the state current.
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