利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.022 秒)

    INERTIAL SENSOR
    1.
    发明申请
    INERTIAL SENSOR 审中-公开
    惯性传感器

    公开(公告)号：US20120125096A1

    公开(公告)日：2012-05-24

    申请号：US13283517

    申请日：2011-10-27

    申请人： Heung Woo Park ,  Won Kyu Jeung ,  Hyun Kee Lee ,  Si Joong Yang

    发明人： Heung Woo Park ,  Won Kyu Jeung ,  Hyun Kee Lee ,  Si Joong Yang

    IPC分类号： G01C19/56

    CPC分类号： G01C19/5783

    摘要： Disclosed herein is an inertial sensor which includes a sensing unit including a mass mounted to be displaced on a flexible substrate part, a driving unit moving the mass, and a displacement detecting unit detecting a displacement of the mass, the inertial sensor comprising: a top cap covering a top of the flexible substrate part; and a bottom cap covering a bottom of the mass. Thereby, the inertial sensor can be implemented in an economic EMC molding package shape, while protecting the mass and the piezo-electric element. Further, the inertial sensor optimizes a thickness of the cap covering the mass and the piezo-electric element and an interval between the mass and the piezo-electric element to have improved freedom in design of space utilization as well as improved driving characteristics and Q values.

    摘要翻译： 本文公开了一种惯性传感器，其包括感测单元，该感测单元包括安装成在柔性基板部件上移位的质量，移动该质量块的驱动单元和检测该质量块的位移的位移检测单元，该惯性传感器包括：顶部 帽盖覆盖柔性基板部分的顶部; 以及覆盖该质量块底部的底盖。 因此，惯性传感器可以以经济的EMC成型包装形式实现，同时保护质量和压电元件。 此外，惯性传感器优化覆盖质量块和压电元件的盖的厚度以及质量块和压电元件之间的间隔，以提高空间利用设计的自由度以及改善的驱动特性和Q值 。

    Wafer-level image sensor module, method of manufacturing the same and camera module
    2.
    发明申请
    Wafer-level image sensor module, method of manufacturing the same and camera module 审中-公开
    晶圆级图像传感器模块，其制造方法和相机模块

    公开(公告)号：US20110012220A1

    公开(公告)日：2011-01-20

    申请号：US12923454

    申请日：2010-09-22

    申请人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

    发明人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

    IPC分类号： H01L31/0203

    CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599

    摘要： A wafer-level image sensor module including: a wafer having an image sensor and a plurality of upper pads provided thereon, the wafer having an inclined surface on either side thereof; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of lead portions having one ends connected to the respective upper pads, the lead portions being formed to extend to the bottom surface of the wafer along the inclined surface of the wafer; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the other ends of the respective lead portions

    摘要翻译： 一种晶片级图像传感器模块，包括：具有图像传感器和设置在其上的多个上焊盘的晶片，所述晶片在其两侧具有倾斜表面; 透明构件安装在晶片的顶表面上方，以密封图像传感器; 多个引线部分，其一端连接到相应的上焊盘，引线部分形成为沿着晶片的倾斜表面延伸到晶片的底表面; 形成在所述晶片的上表面上以便位于所述透明构件外部的封装部; 以及多个外部连接构件，其电连接到各个引线部分的另一端

    Wafer level package fabrication method
    5.
    发明授权
    Wafer level package fabrication method 有权
    晶圆级封装制造方法

    公开(公告)号：US07696004B2

    公开(公告)日：2010-04-13

    申请号：US12155317

    申请日：2008-06-02

    申请人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    发明人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L23/10 ,  H01L21/76898 ,  H01L2924/0002 ,  H03H9/105 ,  H03H9/1092 ,  H01L2924/00

    摘要： Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.

    摘要翻译： 提供了晶片级封装制造方法。 该方法包括提供在其上表面上包括一个或多个器件的器件衬底晶片和电连接到该器件的焊盘，提供围绕该焊盘的器件的接合密封，将盖衬底晶片接合到器件衬底 晶片通过接合密封，所述盖基板晶片具有形成在与所述接合焊盘相对应的区域中的通孔，在所述盖基板晶片上形成外部端子，所述外部端子电连接到所述接合焊盘，以及切割所述盖基板晶片 以及沿着切割线的装置基板晶片，以单独分离多个晶片级封装。 该方法有利于减小产品尺寸以实现小型化，能够进行没有晶片变形或损坏的接合工艺，并增加晶片材料选择的自由度。

    Wafer level package fabrication method
    6.
    发明申请
    Wafer level package fabrication method 有权
    晶圆级封装制造方法

    公开(公告)号：US20080299706A1

    公开(公告)日：2008-12-04

    申请号：US12155317

    申请日：2008-06-02

    申请人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    发明人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    IPC分类号： H01L21/50

    CPC分类号： H01L23/10 ,  H01L21/76898 ,  H01L2924/0002 ,  H03H9/105 ,  H03H9/1092 ,  H01L2924/00

    摘要： Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.

    摘要翻译： 提供了晶片级封装制造方法。 该方法包括提供在其上表面上包括一个或多个器件的器件衬底晶片和电连接到该器件的焊盘，提供围绕该焊盘的器件的接合密封，将盖衬底晶片接合到器件衬底 晶片通过接合密封，所述盖基板晶片具有形成在与所述接合焊盘相对应的区域中的通孔，在所述盖基板晶片上形成外部端子，所述外部端子电连接到所述接合焊盘，以及切割所述盖基板晶片 以及沿着切割线的装置基板晶片，以单独分离多个晶片级封装。 该方法有利于减小产品尺寸以实现小型化，能够进行没有晶片变形或损坏的接合工艺，并增加晶片材料选择的自由度。

    Wafer-level package and method of manufacturing the same
    8.
    发明申请
    Wafer-level package and method of manufacturing the same 审中-公开
    晶圆级封装及其制造方法

    公开(公告)号：US20090085204A1

    公开(公告)日：2009-04-02

    申请号：US12216630

    申请日：2008-07-08

    申请人： Seung Wook Park ,  Chun Choi ,  Ju Pyo Hong ,  Si Joong Yang ,  Dae Jun Kim

    发明人： Seung Wook Park ,  Chun Choi ,  Ju Pyo Hong ,  Si Joong Yang ,  Dae Jun Kim

    IPC分类号： H01L21/56 ,  H01L23/498

    CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L23/315 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a wafer-level package including a wafer-level semiconductor chip having a plurality of integrated circuits (ICs) and pads formed on the top surface thereof; a molding material of which the outer portion is supported by the top surface of the semiconductor chip such that a cavity is provided on the semiconductor chip; and a conducive member filled in a plurality of vias which are formed in arbitrary positions of the molding material so as to pass through the molding material, the conductive member being connected to the pads.

    摘要翻译： 提供了一种晶片级封装，其包括具有形成在其顶表面上的多个集成电路（IC）和焊盘的晶片级半导体芯片; 外部由半导体芯片的上表面支撑的成型材料，使得在半导体芯片上设置空腔; 以及填充有多个通孔的导电构件，其形成在模制材料的任意位置以便通过模制材料，导电构件连接到垫。