公开(公告)号：US20180174998A1

公开(公告)日：2018-06-21

申请号：US15802941

申请日：2017-11-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Kaisei SATO ,  Keita HATASA ,  Tomomi OKUMURA

IPC分类号： H01L23/00

CPC分类号： H01L24/85 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/91 ,  H01L24/92 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/271 ,  H01L2224/2741 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/48847 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2224/85048 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85447 ,  H01L2224/92165 ,  H01L2224/9221 ,  H01L2224/92247 ,  H01L2924/00015 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/365 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Method for manufacturing a semiconductor device includes: preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the second conductive member and preliminary solder is provided on a lower surface of the conductive spacer; preparing a second subassembly in which the lower surface of the semiconductor element is soldered on the first conductive member and the bonding wire is joined on upper surface of the semiconductor element; and soldering the upper surface of the semiconductor element in the second subassembly on the lower surface of the conducive spacer in the first subassembly by melting the preliminary solder in the first subassembly

公开(公告)号：US20170162403A1

公开(公告)日：2017-06-08

申请号：US15439817

申请日：2017-02-22

申请人： VISHAY-SILICONIX

发明人： Kyle TERRILL ,  Frank KUO ,  Sen MAO

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L21/56

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

公开(公告)号：US20170117209A1

公开(公告)日：2017-04-27

申请号：US15129250

申请日：2015-03-26

申请人： HERAEUS DEUTSCHLAND GMBH & CO. KG

发明人： Michael BENEDIKT ,  Thomas KREBS ,  Michael SCHÄFER ,  Wolfgang SCHMITT ,  Andreas HINRICH ,  Andreas KLEIN ,  Alexander BRAND ,  Martin BLEIFUSS

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49513 ,  H01L21/4821 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27505 ,  H01L2224/27848 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/371 ,  H01L2224/37639 ,  H01L2224/4005 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/9221 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00012

摘要： A carrier and the clip are used to produce a packaging having a lead frame by connection to the chip using sintering of the solidified sintering pastes in one work step. The carrier may be a lead frame and a clip for at least one semiconductor element has at least one functional surface for connecting to the semiconductor element and a plurality of connections. The material of the carrier or of the clip includes a metal and a layer made of a solidified sintering paste. The sintering paste may contain silver and/or a silver compound. The sintering paste is arranged on the functional surface. The carrier or clip and the layer made of sintering paste form an intermediate product that can be connected to the semiconductor element.

公开(公告)号：US09589929B2

公开(公告)日：2017-03-07

申请号：US13830041

申请日：2013-03-14

申请人： VISHAY-SILICONIX

发明人： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/31

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

摘要翻译： 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。

公开(公告)号：US20150249061A1

公开(公告)日：2015-09-03

申请号：US14715484

申请日：2015-05-18

申请人： Broadcom Corporation

发明人： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

公开(公告)号：US20150102360A1

公开(公告)日：2015-04-16

申请号：US14577875

申请日：2014-12-19

申请人： Avogy, Inc.

发明人： Brian Joel Alvarez ,  Donald R. Disney ,  Hui Nie ,  Patrick James Lazlo Hyland

IPC分类号： H01L29/20 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/47

CPC分类号： H01L29/2003 ,  H01L21/28575 ,  H01L21/28581 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/452 ,  H01L29/475 ,  H01L29/4958 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03848 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/06181 ,  H01L2224/09181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/9202 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01009 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/04941 ,  H01L2224/37099 ,  H01L2224/37599 ,  H01L2924/206

摘要： An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

摘要翻译： 半导体器件的实施例包括具有第一表面和第二表面的氮化镓（GaN）衬底。 第二表面基本上与第一表面相对，至少一个器件层耦合到第一表面，并且背面金属耦合到第二表面。 顶部金属叠层耦合到至少一个器件层。 顶部金属堆叠包括耦合到至少一个器件层的表面的接触金属，耦合到接触金属的保护层，耦合到保护层的扩散阻挡层以及耦合到扩散阻挡层的焊盘金属。 半导体器件被配置为在顶部金属堆叠和背面金属之间导电。

公开(公告)号：US20150076570A1

公开(公告)日：2015-03-19

申请号：US14127187

申请日：2013-05-27

申请人： NSK LTD.

发明人： Takashi Sunaga ,  Noboru Kaneko ,  Osamu Miyoshi

IPC分类号： H01L23/00 ,  H01L29/78

CPC分类号： H01L24/43 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/77 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L29/78 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/41175 ,  H01L2224/43848 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/494 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/75272 ,  H01L2224/77272 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/85 ,  H01L2224/85815 ,  H01L2224/9221 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/1031 ,  H05K2201/10409 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/33 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/48227

摘要： There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or other surface mounting devices on the wiring patterns on the substrate. A semiconductor module includes: a plurality of wiring patterns formed on an insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder.

摘要翻译： 提供了一种半导体模块及其制造方法，其可以通过焊接安装操作将裸芯片晶体管的电极和布线图案与基板上的布线图案相连接，在相同的焊接安装操作过程中， 裸芯片晶体管或其他表面安装器件在基板上的布线图案上。 半导体模块包括：形成在绝缘层上的多个布线图案; 通过焊料在多个布线图案中安装在一个布线图案上的裸芯片晶体管; 以及铜连接器，其由用于通过焊料将形成在裸芯片晶体管的顶表面上的电极和多个布线图案中的另一布线图案连接的铜板构成。

公开(公告)号：US20150048493A1

公开(公告)日：2015-02-19

申请号：US14318643

申请日：2014-06-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Tae-Hong MIN ,  Young-Kun JEE ,  Tae-Je CHO

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/373

CPC分类号： H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92225 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07802

摘要： In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

摘要翻译： 在一个实施例中，半导体封装包括电路基板，堆叠在电路基板上的多个半导体芯片，插入在半导体芯片之间的绝缘粘合剂图案，设置在最上半导体芯片上的散热片，并通过 散热粘合剂图案，以及设置在电路基板上以覆盖半导体芯片的侧壁，绝缘粘合剂图案，散热粘合剂图案和热块的模具结构。 在模具结构的制造过程中半导体封装的故障可能会降低。 因此，半导体封装可具有良好的工作特性和可靠性。

公开(公告)号：US20140070226A1

公开(公告)日：2014-03-13

申请号：US13611467

申请日：2012-09-12

申请人： Brian Joel Alvarez ,  Donald R. Disney ,  Hui Nie ,  Patrick James Lazlo Hyland

发明人： Brian Joel Alvarez ,  Donald R. Disney ,  Hui Nie ,  Patrick James Lazlo Hyland

IPC分类号： H01L29/20 ,  H01L21/768

CPC分类号： H01L29/2003 ,  H01L21/28575 ,  H01L21/28581 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/452 ,  H01L29/475 ,  H01L29/4958 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03848 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/06181 ,  H01L2224/09181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/9202 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01009 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/04941 ,  H01L2224/37099 ,  H01L2224/37599

摘要： An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

摘要翻译： 半导体器件的实施例包括具有第一表面和第二表面的氮化镓（GaN）衬底。 第二表面基本上与第一表面相对，至少一个器件层耦合到第一表面，并且背面金属耦合到第二表面。 顶部金属叠层耦合到至少一个器件层。 顶部金属堆叠包括耦合到至少一个器件层的表面的接触金属，耦合到接触金属的保护层，耦合到保护层的扩散阻挡层以及耦合到扩散阻挡层的焊盘金属。 半导体器件被配置为在顶部金属堆叠和背面金属之间导电。

公开(公告)号：US20130127049A1

公开(公告)日：2013-05-23

申请号：US13716844

申请日：2012-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Dean Wang ,  Chien-Hsiun Lee ,  Clinton Chao ,  Mirng-Ji Lii ,  Tjandra Winata Karta

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8321 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

摘要： A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure.

摘要翻译： 一种具有第一器件的半导体器件，包括第一穿透硅通孔（TSV）结构，第一涂层材料设置在所述第一器件上，所述第一涂覆材料连续地延伸到所述第一器件上并覆盖所述第一TSV结构， 设置在所述第一装置上并且在所述第一涂层材料内的所述第二装置，所述第二装置包括第二TSV结构和多个导电凸块，所述多个导电凸块定位在所述第一涂层材料内，第二涂层材料设置在所述第二装置上 所述第二涂层材料连续地延伸到所述第二装置上并覆盖所述第二TSV结构，以及设置在所述第二涂层材料上的第三装置，所述第三装置包括第三TSV结构。