公开(公告)号：US20090085134A1

公开(公告)日：2009-04-02

申请号：US12007977

申请日：2008-01-17

申请人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

发明人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

IPC分类号： H01L31/0232 ,  H01L21/52

CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599

摘要： Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the transparent member; a plurality of upper pads formed on the upper ends of the respective vias; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the lower ends of the respective vias.

摘要翻译： 提供了一种晶片级图像传感器模块，其包括晶片; 安装在晶片上的图像传感器; 透明构件安装在晶片的顶表面上方，以密封图像传感器; 形成在所述晶片中以便位于所述透明构件外部的多个通孔; 形成在各个通路的上端的多个上焊盘; 形成在所述晶片的上表面上以便位于所述透明构件外部的封装部; 以及电连接到各个通孔的下端的多个外部连接构件。

公开(公告)号：US20110012220A1

公开(公告)日：2011-01-20

申请号：US12923454

申请日：2010-09-22

申请人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

发明人： Seung Wook Park ,  Jing Li Yuan ,  Ju Pyo Hong ,  Si Joong Yang

IPC分类号： H01L31/0203

CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A wafer-level image sensor module including: a wafer having an image sensor and a plurality of upper pads provided thereon, the wafer having an inclined surface on either side thereof; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of lead portions having one ends connected to the respective upper pads, the lead portions being formed to extend to the bottom surface of the wafer along the inclined surface of the wafer; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the other ends of the respective lead portions

摘要翻译： 一种晶片级图像传感器模块，包括：具有图像传感器和设置在其上的多个上焊盘的晶片，所述晶片在其两侧具有倾斜表面; 透明构件安装在晶片的顶表面上方，以密封图像传感器; 多个引线部分，其一端连接到相应的上焊盘，引线部分形成为沿着晶片的倾斜表面延伸到晶片的底表面; 形成在所述晶片的上表面上以便位于所述透明构件外部的封装部; 以及多个外部连接构件，其电连接到各个引线部分的另一端

公开(公告)号：US20080286904A1

公开(公告)日：2008-11-20

申请号：US12153378

申请日：2008-05-16

申请人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

发明人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

IPC分类号： H01L21/60

CPC分类号： H03H9/1092 ,  H01L23/10 ,  H01L24/14 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/17515 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.

摘要翻译： 提供一种半导体封装的制造方法。 在该方法中，设置用于盖基板的晶片。 用于盖基板的晶片在下表面上包括多个通孔和通孔电极。 提供了用于器件衬底的晶片。 用于器件衬底的晶片包括上表面上的电路单元和连接电极。 用于盖衬底的晶片和用于器件衬底的晶片主要通过主要粘合剂的介质粘合。 形成沟槽，以将器件基板的晶片的上表面沿初级粘合剂的外边缘暴露于外部。 通过二次粘合剂的介质进行二次接合操作，以电连接通孔电极和连接电极。 用于器件衬底的晶片沿虚拟切割线切割。

公开(公告)号：US07670878B2

公开(公告)日：2010-03-02

申请号：US12153378

申请日：2008-05-16

申请人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

发明人： Jing Li Yuan ,  Jae Cheon Doh ,  Tae Hoon Kim ,  Si Joong Yang ,  Seung Wook Park

IPC分类号： H01L21/44

CPC分类号： H03H9/1092 ,  H01L23/10 ,  H01L24/14 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/17515 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.

摘要翻译： 提供一种半导体封装的制造方法。 在该方法中，设置用于盖基板的晶片。 用于盖基板的晶片在下表面上包括多个通孔和通孔电极。 提供了用于器件衬底的晶片。 用于器件衬底的晶片包括上表面上的电路单元和连接电极。 用于盖衬底的晶片和用于器件衬底的晶片主要通过主要粘合剂的介质粘合。 形成沟槽，以将器件基板的晶片的上表面沿初级粘合剂的外边缘暴露于外部。 通过二次粘合剂的介质进行二次接合操作，以电连接通孔电极和连接电极。 用于器件衬底的晶片沿虚拟切割线切割。

公开(公告)号：US08704350B2

公开(公告)日：2014-04-22

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US20100117218A1

公开(公告)日：2010-05-13

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/29

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。