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30 条记录 (耗时 0.021 秒)

    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook
    2.
    发明授权
    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
    半导体存储器，运动图像存储存储器，运动图像存储装置，运动图像显示装置，静态图像存储存储器和电子笔记本

    公开(公告)号：US6023440A

    公开(公告)日：2000-02-08

    申请号：US320577

    申请日：1999-05-27

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

    CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

    摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

    摘要翻译： 分割成多个子存储器阵列的存储器阵列设置在芯片上，使得如果通过子存储器阵列选择电路选择了指定的子存储器阵列，则执行正常的读取/写入操作， 基于由一组外部地址信号指示的地址对子存储器阵列。 同时，安装在芯片上的用于自刷新的时钟发生器产生用于自刷新的字线基本时钟和用于刷新的字线基本时钟，从而选择子存储阵列中的字线，其中 尚未选中。 在随后选择进行刷新操作的子存储阵列的预定时间之前，输出刷新停止信号，以强制中止刷新操作，从而防止存储单元的充电不足。 多个子存储器阵列中的每一个存储顺序的图像数据组，一帧或一个场上的数据。

    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle
    5.
    发明授权
    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle 失效
    分割的字线存储器布置在连续访问周期期间具有字线重叠的激活

    公开(公告)号：US5699300A

    公开(公告)日：1997-12-16

    申请号：US341947

    申请日：1994-11-16

    申请人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/409 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1015 ,  G11C8/14 ,  G11C8/18

    摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

    摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。 由列寻址选择的读出放大器的输出信号被传送到相应的数据线。 分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。 感测放大器被分组成具有相应公共列地址的多个组。 每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

    Static random access memory capable of reducing stendly power consumption and off-leakage current
    6.
    发明授权
    Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
    静态随机存取存储器能够降低待机功耗和漏电流

    公开(公告)号：US5764566A

    公开(公告)日：1998-06-09

    申请号：US893682

    申请日：1997-07-11

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory
    8.
    发明授权
    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
    数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器

    公开(公告)号：US5680366A

    公开(公告)日：1997-10-21

    申请号：US573133

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。