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    Method for producing a gate cut structure on an array of semiconductor fins
    1.
    发明授权
    Method for producing a gate cut structure on an array of semiconductor fins 有权

    公开(公告)号：US10978335B2

    公开(公告)日：2021-04-13

    申请号：US16563747

    申请日：2019-09-06

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

    IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

    Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

    Area-selective deposition of a tantalum silicide TaSix mask material
    2.
    发明授权
    Area-selective deposition of a tantalum silicide TaSix mask material 有权

    公开(公告)号：US10784158B2

    公开(公告)日：2020-09-22

    申请号：US16412923

    申请日：2019-05-15

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez

    IPC: H01L21/768 ,  H01L21/311

    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.

    Plasma method for reducing post-lithography line width roughness
    5.
    发明授权
    Plasma method for reducing post-lithography line width roughness 有权
    等离子体方法，用于减小光刻后线宽度粗糙度

    公开(公告)号：US09520298B2

    公开(公告)日：2016-12-13

    申请号：US14616672

    申请日：2015-02-07

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Peter De Schepper ,  Jean-Francois de Marneffe ,  Efrain Altamirano Sanchez

    IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/027

    CPC classification number: H01L21/3086 ,  H01L21/0273

    Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and −110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30s.

    Abstract translation: 本公开涉及一种用于处理衬底上的光致抗蚀剂结构的方法，所述方法包括在衬底上制造一个或多个抗蚀剂结构，将衬底引入等离子体反应器中，并使衬底在较低温度下进行等离子体处理 例如在零到-110℃之间。等离子体处理可以是在电感耦合等离子体反应器中进行的H 2等离子体处理。 治疗时间可能至少为30s。

    Decreasing the Critical Dimensions in Integrated Circuits
    6.
    发明申请
    Decreasing the Critical Dimensions in Integrated Circuits 有权
    降低集成电路中的关键尺寸

    公开(公告)号：US20160181090A1

    公开(公告)日：2016-06-23

    申请号：US14977146

    申请日：2015-12-21

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Efrain Altamirano Sanchez ,  Farrukh Qayyum Yasin ,  Raven Demeyer

    IPC: H01L21/02 ,  H01L29/06 ,  H01L21/027 ,  H01L21/311 ,  H01L21/324

    CPC classification number: H01L21/02348 ,  G03F7/0002 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/02282 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/0657

    Abstract: A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.

    Abstract translation: 描述了用于基板的平版印刷图案化的方法。 该方法包括获得待图案化的基底。 其还包括随后执行以下循环的至少两次：施加用于形成金属氧化物图案的可热收缩的金属氧化物层的光刻图案化工艺，并且热收缩金属氧化物图案。 在至少两个循环期间形成的不同的金属氧化物图案被定位成彼此靠近，使得收缩的金属氧化物图案一起形成要转移到基底的整体图案。 在执行循环至少两次之后，将总体图案转移到基底。

    Plasma Method for Reducing Post-Lithography Line Width Roughness
    7.
    发明申请
    Plasma Method for Reducing Post-Lithography Line Width Roughness 有权
    等离子体方法减少后平版印刷线宽度粗糙度

    公开(公告)号：US20150228497A1

    公开(公告)日：2015-08-13

    申请号：US14616672

    申请日：2015-02-07

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Peter De Schepper ,  Jean-Francois de Marneffe ,  Efrain Altamirano Sanchez

    IPC: H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/3086 ,  H01L21/0273

    Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and −110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30 s.

    Abstract translation: 本公开涉及一种用于处理衬底上的光致抗蚀剂结构的方法，所述方法包括在衬底上制造一个或多个抗蚀剂结构，将衬底引入等离子体反应器中，并使衬底在较低温度下进行等离子体处理 例如在零到-110℃之间。等离子体处理可以是在电感耦合等离子体反应器中进行的H 2等离子体处理。 治疗时间可以至少30秒。

    METHODS OF SEMICONDUCTOR DEVICE PROCESSING
    8.
    发明申请
    METHODS OF SEMICONDUCTOR DEVICE PROCESSING 有权

    公开(公告)号：US20210193510A1

    公开(公告)日：2021-06-24

    申请号：US17119802

    申请日：2020-12-11

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Geert Mannaert

    IPC: H01L21/762 ,  H01L21/8234

    Abstract: According to an aspect of the disclosed technology, there is provided a method comprising: providing a substrate, the substrate supporting an STI-layer and a set of fin structures, each fin structure comprising an upper portion protruding above the STI-layer, forming a spacer layer over the upper portions of the set of fin structures and the STI-layer, forming a sacrificial layer over the spacer layer, the sacrificial layer at least partially embedding the upper portions of the fin structures, partially etching back the sacrificial layer to expose spacer layer portions above upper surfaces of the upper portions of the set of fin structures, and etching the spacer layer and exposing at least the upper surfaces of the upper portions of the set of fin structures, while the sacrificial layer at least partially masks spacer layer portions above the STI-layer.

    METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECTIONS FOR CONTACTING A FET TRANSISTOR
    9.
    发明申请
    METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECTIONS FOR CONTACTING A FET TRANSISTOR 有权

    公开(公告)号：US20210126108A1

    公开(公告)日：2021-04-29

    申请号：US17083125

    申请日：2020-10-28

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

    IPC: H01L29/66 ,  H01L21/768

    Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

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