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    Data rate programming using source degenerated CTLE
    2.
    发明授权
    Data rate programming using source degenerated CTLE 有权
    使用源退化CTLE的数据速率编程

    公开(公告)号：US09225560B1

    公开(公告)日：2015-12-29

    申请号：US14681989

    申请日：2015-04-08

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04L25/06 ,  H04L25/10 ,  H04L25/03 ,  H03K17/687

    CPC classification number: H04L25/03885 ,  H03K17/687 ,  H04B10/58 ,  H04B10/6163 ,  H04L25/03019

    Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 在各种实施例中，本发明提供一种通过改变其负载电阻和源极电阻的电阻值来改变输出频率响应的CML器件。 使用偏置控制电压来调整CML器件的尾部电流，尾电流调节CML器件的输出增益。 还有其它实施例。

    High-speed clock skew correction for serdes receivers
    3.
    发明授权
    High-speed clock skew correction for serdes receivers 有权
    针对serdes接收机的高速时钟偏移校正

    公开(公告)号：US09209962B1

    公开(公告)日：2015-12-08

    申请号：US14715494

    申请日：2015-05-18

    Applicant: Inphi Corporation

    Inventor： Parmanand Mishra ,  Simon Forey

    IPC: H04L7/00 ,  H04L7/033 ,  H04B1/10

    CPC classification number: H04L7/0079 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/0807 ,  H04B1/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/06 ,  H04L7/10

    Abstract: The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明提供了一种用于确定最小化由于边缘样本和数据样本之间的不良对准导致的偏斜误差的调整延迟的机制。 调整延迟由采样边缘样本和采样频率不同的不同测试延迟采样数据样本确定。 选择与数据样本和边缘样本之间的最小平均位置相关联的测试延迟作为调整延迟。 当以采样频率采样数据时，调整延迟用作参数。 还有其它实施例。

    Serializer/deserializer apparatus with loopback configuration and methods thereof
    4.
    发明授权
    Serializer/deserializer apparatus with loopback configuration and methods thereof 有权
    具有环回配置的串行器/解串器设备及其方法

    公开(公告)号：US08964820B2

    公开(公告)日：2015-02-24

    申请号：US14479121

    申请日：2014-09-05

    Applicant: Inphi Corporation

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04B1/38 ,  H04L25/06 ,  H04B3/04

    CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

    Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

    Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

    Variable gain amplifiers for communication systems
    6.
    发明授权
    Variable gain amplifiers for communication systems 有权

    公开(公告)号：US10270409B1

    公开(公告)日：2019-04-23

    申请号：US15597074

    申请日：2017-05-16

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03F3/45 ,  H03G3/22 ,  H03G3/30 ,  H03G7/06 ,  H03G1/00

    Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

    Charge pump circuits for clock and data recovery
    7.
    发明授权
    Charge pump circuits for clock and data recovery 有权

    公开(公告)号：US10243570B1

    公开(公告)日：2019-03-26

    申请号：US15663419

    申请日：2017-07-28

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Parmanand Mishra ,  Michael Harwood ,  Rajasekhar Nagulapalli

    IPC: H03L7/06 ,  H03L7/08 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H03L7/187 ,  H03K5/135

    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

    Compact high speed duty cycle corrector
    8.
    发明授权
    Compact high speed duty cycle corrector 有权

    公开(公告)号：US10122368B2

    公开(公告)日：2018-11-06

    申请号：US15840984

    申请日：2017-12-13

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03K5/156 ,  H03L7/08 ,  H04L27/01 ,  H03G3/20

    Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    Loss of signal detection on CDR
    10.
    发明授权
    Loss of signal detection on CDR 有权

    公开(公告)号：US10044497B2

    公开(公告)日：2018-08-07

    申请号：US15337072

    申请日：2016-10-28

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Simon Forey

    IPC: H03D3/24 ,  H04L7/033 ,  H04L25/02 ,  H04L12/26 ,  H03L7/00 ,  H04L7/00 ,  H04B17/318 ,  H04L27/01 ,  H03M9/00

    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

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