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    PILLAR SELECT TRANSISTOR FOR 3-DIMENSIONAL CROSS POINT MEMORY
    1.
    发明申请
    PILLAR SELECT TRANSISTOR FOR 3-DIMENSIONAL CROSS POINT MEMORY 有权

    公开(公告)号：US20220190030A1

    公开(公告)日：2022-06-16

    申请号：US17118385

    申请日：2020-12-10

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Derchang Kau ,  Max Hineman

    IPC: H01L27/24 ,  H01L27/06 ,  G11C13/00 ,  H01L45/00 ,  G11C5/06

    Abstract: A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.

    TIER ARCHITECTURE FOR 3-DIMENSIONAL CROSS POINT MEMORY
    2.
    发明申请
    TIER ARCHITECTURE FOR 3-DIMENSIONAL CROSS POINT MEMORY 有权

    公开(公告)号：US20220190029A1

    公开(公告)日：2022-06-16

    申请号：US17118367

    申请日：2020-12-10

    Applicant: Intel Corporation

    Inventor： Derchang Kau ,  Prashant Majhi ,  Khaled Hasnat

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory structure includes a plurality of memory cells between a first and a second terminal and a pair of first conductors within a first tier, where individual ones of the first conductors are coupled to the first terminal of a first adjacent pair of memory cells in a first row orthogonal to the first conductors. The memory structure further includes a pair of second conductors within a second tier and parallel to the first conductors, where individual ones of the second conductors are coupled to the first terminal of a second adjacent pair of memory cells in a second row. The memory structure further includes a third conductor between the first and second tiers, and between each of the pair of the first conductors and the pair of the second conductors. The third conductor is coupled to second terminals of both the first and second adjacent pairs of memory cells.

    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY
    4.
    发明申请
    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY 有权
    跨点存储器中的参考架构

    公开(公告)号：US20160093375A1

    公开(公告)日：2016-03-31

    申请号：US14850152

    申请日：2015-09-10

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

    Reference architecture in a cross-point memory
    9.
    发明授权
    Reference architecture in a cross-point memory 有权
    参考架构在交叉点内存中

    公开(公告)号：US09142271B1

    公开(公告)日：2015-09-22

    申请号：US14313695

    申请日：2014-06-24

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

    Bipolar decoder for crosspoint memory
    10.
    发明授权
    Bipolar decoder for crosspoint memory 有权

    公开(公告)号：US11900998B2

    公开(公告)日：2024-02-13

    申请号：US16948300

    申请日：2020-09-11

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Sandeep Kumar Guliani ,  Mase J. Taub ,  Derchang Kau ,  Ashir G. Shah

    IPC: G11C8/08 ,  G11C13/00

    CPC classification number: G11C13/0028 ,  G11C13/0026

    Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

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