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    Inexpensive electrode materials to facilitate rutile phase titanium oxide
    2.
    发明授权
    Inexpensive electrode materials to facilitate rutile phase titanium oxide 有权
    廉价的电极材料，以促进金红石相氧化钛

    公开(公告)号：US08980744B2

    公开(公告)日：2015-03-17

    申请号：US13675852

    申请日：2012-11-13

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L27/108 ,  H01L49/02 ,  C23C16/40

    CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

    Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

    Band gap improvement in DRAM capacitors
    3.
    发明授权
    Band gap improvement in DRAM capacitors 有权
    DRAM电容器带隙改善

    公开(公告)号：US08878269B2

    公开(公告)日：2014-11-04

    申请号：US13738831

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

    IPC: H01L27/108

    CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

    Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

    Blocking layers for leakage current reduction in DRAM devices
    4.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权

    公开(公告)号：US08569818B2

    公开(公告)日：2013-10-29

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/94 ,  H01L21/20

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    High performance dielectric stack for DRAM capacitor
    5.
    发明授权
    High performance dielectric stack for DRAM capacitor 有权
    用于DRAM电容器的高性能电介质堆叠

    公开(公告)号：US08546236B2

    公开(公告)日：2013-10-01

    申请号：US13738866

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/20 ,  H01L21/31

    CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

    Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

    Blocking Layers for Leakage Current Reduction in DRAM Devices
    8.
    发明申请
    Blocking Layers for Leakage Current Reduction in DRAM Devices 有权
    阻止DRAM器件泄漏电流降低的层

    公开(公告)号：US20130113079A1

    公开(公告)日：2013-05-09

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    High temperature ALD process for metal oxide for DRAM applications
    10.
    发明授权
    High temperature ALD process for metal oxide for DRAM applications 有权
    用于DRAM应用的金属氧化物的高温ALD工艺

    公开(公告)号：US08829647B2

    公开(公告)日：2014-09-09

    申请号：US13737156

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Edward Haywood ,  Sandra Malhotra ,  Hiroyuki Ode

    IPC: H01L29/92 ,  C23C16/455 ,  H01L21/285 ,  H01L49/02

    CPC classification number: H01L29/92 ,  C23C16/45525 ,  H01L21/28562 ,  H01L28/65 ,  H01L28/75

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层含有使用高温低压ALD工艺形成的导电金属氧化物。 高温ALD工艺产生了具有增强的结晶度，较高密度，降低的收缩率和较低的碳污染的层。 高温ALD工艺可以用于底部电极和顶部电极层中的一个或两个。

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