公开(公告)号：US20240347618A1

公开(公告)日：2024-10-17

申请号：US18755189

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/517 ,  H01L27/0886 ,  H01L29/42364

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.

公开(公告)号：US20250113586A1

公开(公告)日：2025-04-03

申请号：US18374929

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul PANDEY ,  Yang CAO ,  Rahul RAMAMURTHY ,  Jubin NATHAWAT ,  Michael L. HATTENDORF ,  Jae HUR ,  Anant H. JAHAGIRDAR ,  Steven R. NOVAK ,  Tao CHU ,  Yanbin LUO ,  Minwoo JANG ,  Paul A. PACKAN ,  Owen Y. LOH ,  David J. TOWNER

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.

公开(公告)号：US20240312991A1

公开(公告)日：2024-09-19

申请号：US18121720

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  David J. TOWNER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having tuned upper nanowires are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material.

公开(公告)号：US20230290852A1

公开(公告)日：2023-09-14

申请号：US17694170

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  David J. TOWNER ,  David N. GOLDSTEIN ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.

公开(公告)号：US20240395695A1

公开(公告)日：2024-11-28

申请号：US18794584

申请日：2024-08-05

Applicant: Intel Corporation

Inventor： Aaron J. WELSH ,  Christopher M. PELTO ,  David J. TOWNER ,  Mark A. BLOUNT ,  Takayoshi ITO ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Stephanie F. SUNDHOLM ,  Chamara ABEYSEKERA ,  Anil W. DEY ,  Che-Yun LIN ,  Uygar E. AVCI

IPC: H01L23/522

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：US20230420531A1

公开(公告)日：2023-12-28

申请号：US17850769

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Orb ACTON ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/0673

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a first N-type dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the first N-type dipole material layer and a second N-type dipole material layer.

公开(公告)号：US20240332394A1

公开(公告)日：2024-10-03

申请号：US18129651

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： David N. GOLDSTEIN ,  David J. TOWNER ,  Dax M. CRUM ,  Omair SAADAT ,  Dan S. LAVRIC ,  Orb ACTON ,  Tongtawee WACHARASINDHU ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A PMOS gate stack is over the first vertical arrangement of horizontal nanowires, the PMOS gate stack having a multi-layer molybdenum structure on a first gate dielectric. An NMOS gate stack is over the second vertical arrangement of horizontal nanowires, the NMOS gate stack having the multi-layer molybdenum structure or an N-type conductive layer on a second gate dielectric.

公开(公告)号：US20230317807A1

公开(公告)日：2023-10-05

申请号：US17693150

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having additive gate structures in a tub architecture are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material layer. A dielectric wall is between and in contact with the P-type gate stack and the N-type gate stack.

公开(公告)号：US20220102343A1

公开(公告)日：2022-03-31

申请号：US17033440

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Anthony V. MULE' ,  David J. TOWNER ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Angel AQUINO GONZALEZ

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/417 ,  H01L29/78

Abstract: Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.

公开(公告)号：US20250133811A1

公开(公告)日：2025-04-24

申请号：US19000050

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H10D64/68 ,  H10D64/27 ,  H10D84/83

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.