公开(公告)号：US20250113586A1

公开(公告)日：2025-04-03

申请号：US18374929

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul PANDEY ,  Yang CAO ,  Rahul RAMAMURTHY ,  Jubin NATHAWAT ,  Michael L. HATTENDORF ,  Jae HUR ,  Anant H. JAHAGIRDAR ,  Steven R. NOVAK ,  Tao CHU ,  Yanbin LUO ,  Minwoo JANG ,  Paul A. PACKAN ,  Owen Y. LOH ,  David J. TOWNER

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.

公开(公告)号：US20210050448A1

公开(公告)日：2021-02-18

申请号：US17085981

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US20190245088A1

公开(公告)日：2019-08-08

申请号：US16386197

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/267 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US20230253499A1

公开(公告)日：2023-08-10

申请号：US18134418

申请日：2023-04-13

Applicant: Intel Corporation

Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/66492 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7851

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US20160380102A1

公开(公告)日：2016-12-29

申请号：US15038969

申请日：2013-12-27

Applicant: Pratik PATEL ,  Jami A. WIEDEMER ,  Paul A. PACKAN ,  INTEL CORPORATION

Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

IPC: H01L29/78 ,  H01L29/24 ,  H01L21/225 ,  H01L29/66 ,  H01L21/324 ,  H01L29/08 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract translation: 一种方法，包括在鳍片的接合区域中形成开口并在基底上延伸的方法; 在开口中引入掺杂的半导体材料; 并对掺杂的半导体材料进行热处理。 一种方法，包括在从衬底延伸的翅片上形成栅电极; 在所述鳍片的邻近所述栅电极的相对侧上形成开口; 在开口中引入掺杂的半导体材料; 并且热处理足以引起掺杂半导体材料中的掺杂剂扩散的掺杂​​半导体材料。 一种装置，包括横跨从基板延伸的翅片的栅电极; 以及半导体材料填充的开口，在栅电极的相邻相邻两侧的接合区域中，其中半导体材料包括掺杂剂。