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公开(公告)号:US20180068720A1
公开(公告)日:2018-03-08
申请号:US15690148
申请日:2017-08-29
Applicant: Intel Corporation
Inventor: Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0033 , G11C13/0064 , G11C13/0069
Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
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公开(公告)号:US09136873B2
公开(公告)日:2015-09-15
申请号:US13792597
申请日:2013-03-11
Applicant: Intel Corporation
Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。
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公开(公告)号:US10325652B2
公开(公告)日:2019-06-18
申请号:US15690148
申请日:2017-08-29
Applicant: Intel Corporation
Inventor: Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC: G11C13/00
Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
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公开(公告)号:US10088880B2
公开(公告)日:2018-10-02
申请号:US14837372
申请日:2015-08-27
Applicant: Intel Corporation
Inventor: Rajesh Sundaram , Muthukumar P. Swaminathan , Doyle Rivers
Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.
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公开(公告)号:US10056139B2
公开(公告)日:2018-08-21
申请号:US15645990
申请日:2017-07-10
Applicant: Intel Corporation
Inventor: Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
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公开(公告)号:US09934088B2
公开(公告)日:2018-04-03
申请号:US14844843
申请日:2015-09-03
Applicant: Intel Corporation
Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
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公开(公告)号:US09721657B1
公开(公告)日:2017-08-01
申请号:US15089507
申请日:2016-04-02
Applicant: Intel Corporation
Inventor: Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
IPC: G11C13/00
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
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公开(公告)号:US10936418B2
公开(公告)日:2021-03-02
申请号:US16444480
申请日:2019-06-18
Applicant: Intel Corporation
Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
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公开(公告)号:US10062444B2
公开(公告)日:2018-08-28
申请号:US15018109
申请日:2016-02-08
Applicant: Intel Corporation
Inventor: Julie M. Walker , Doyle Rivers
CPC classification number: G11C17/18 , G11C7/20 , G11C16/20 , G11C17/165
Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.
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公开(公告)号:US20160260499A1
公开(公告)日:2016-09-08
申请号:US15018109
申请日:2016-02-08
Applicant: Intel Corporation
Inventor: Julie M. Walker , Doyle Rivers
CPC classification number: G11C17/18 , G11C7/20 , G11C16/20 , G11C17/165
Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.
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