公开(公告)号：US10134758B2

公开(公告)日：2018-11-20

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/768 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US20180294272A1

公开(公告)日：2018-10-11

申请号：US15798352

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Darwin Fan ,  Sateesh Koka ,  Gordon Haller ,  John Hopkins ,  Shyam Surthi ,  Anish Khandekar

IPC: H01L27/11524 ,  H01L21/28 ,  H01L27/11556

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

公开(公告)号：US20180130819A1

公开(公告)日：2018-05-10

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L21/768 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US09741734B2

公开(公告)日：2017-08-22

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US20170170190A1

公开(公告)日：2017-06-15

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  H01L21/768 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.