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公开(公告)号：US20220179797A1
公开(公告)日：2022-06-09
申请号：US17682111
申请日：2022-02-28
Applicant: Intel Corporation
Inventor： Jeffrey C. Swanson , Sreenivas Mandava , Henk Neefs , Jing Ling
IPC: G06F12/0888 , G06F12/1018 , G06F9/46 , G06F9/48
Abstract: An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US20160232063A1
公开(公告)日：2016-08-11
申请号：US14672131
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Debaleena Das , George H. Huang , Jing Ling , Reza E. Daftari , Meera Ganesan
CPC classification number: G06F11/1662 , G06F3/0619 , G06F3/0644 , G06F3/0647 , G06F3/0683 , G06F11/1004 , G06F11/108 , G06F11/1666 , G06F11/20 , G06F11/2094 , G06F2201/825
Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.
Abstract translation: 内存子系统错误管理可实现动态更改的锁步合作伙伴关系。 存储器子系统在第一存储器部分和第二存储器部分之间具有锁步合作关系，以在所述一对存储器资源上扩展纠错。 锁定合作伙伴关系可以预先配置。 响应于检测锁步伙伴关系中的硬错误，存储器子系统可以取消或反转第一存储器部分和第二存储器部分之间的锁步合作关系，并且创建或设置新的锁步伙伴关系。 检测到的错误可能是锁步伙伴关系中的第二个硬错误。 存储器子系统可以在第一存储器部分和第三存储器部分之间创建新的锁步合作关系，作为锁步伙伴，并且在第二存储器部分和作为锁步伙伴的第四存储器部分之间。 内存子系统也可以配置为在更改合作伙伴关系时更改锁步伙伴关系的粒度。
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公开(公告)号：US12235720B2
公开(公告)日：2025-02-25
申请号：US18268956
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Rajat Agarwal , Hsing-Min Chen , Wei P. Chen , Wei Wu , Jing Ling , Kuljit S. Bains , Kjersten E. Criss , Deep K. Buch , Theodros Yigzaw , John G. Holm , Andrew M. Rudoff , Vaibhav Singh , Sreenivas Mandava
IPC: G06F11/10
Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.
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公开(公告)号：US11036634B2
公开(公告)日：2021-06-15
申请号：US16258486
申请日：2019-01-25
Applicant: INTEL CORPORATION
Inventor： Wei Chen , Rajat Agarwal , Jing Ling , Daniel W. Liu
IPC: G06F12/0808 , G06F12/0866 , G06F1/3287 , G06F3/06 , G06F12/06 , G06F12/0811 , G06F12/0868 , G06F12/128 , G06F12/12
Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.
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Patent Agency Ranking
公开(公告)号：US20180165100A1
公开(公告)日：2018-06-14
申请号：US15378878
申请日：2016-12-14
Applicant: Intel Corporation
Inventor： Mahesh S. Natu , Wei Chen , Jing Ling , James E. McCormick, JR.
CPC classification number: G06F9/4406 , G06F11/106
Abstract: An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.
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公开(公告)号：US12242342B2
公开(公告)日：2025-03-04
申请号：US17550859
申请日：2021-12-14
Applicant: Intel Corporation
Inventor： Jing Ling , Wei P. Chen , Rajat Agarwal
Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.
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公开(公告)号：US10346177B2
公开(公告)日：2019-07-09
申请号：US15378878
申请日：2016-12-14
Applicant: Intel Corporation
Inventor： Mahesh S. Natu , Wei Chen , Jing Ling , James E. McCormick, Jr.
IPC: G06F9/44 , G06F9/4401 , G06F11/10
Abstract: An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.
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公开(公告)号：US10198354B2
公开(公告)日：2019-02-05
申请号：US15465513
申请日：2017-03-21
Applicant: INTEL CORPORATION
Inventor： Wei Chen , Rajat Agarwal , Jing Ling , Daniel W. Liu
IPC: G06F12/06 , G06F12/08 , G06F3/06 , G06F12/0808 , G06F12/0811 , G06F12/128 , G06F12/0868
Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.
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公开(公告)号：US09697094B2
公开(公告)日：2017-07-04
申请号：US14672131
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Debaleena Das , George H Huang , Jing Ling , Reza E Daftari , Meera Ganesan
CPC classification number: G06F11/1662 , G06F3/0619 , G06F3/0644 , G06F3/0647 , G06F3/0683 , G06F11/1004 , G06F11/108 , G06F11/1666 , G06F11/20 , G06F11/2094 , G06F2201/825
Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.
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