公开(公告)号：US10790290B2

公开(公告)日：2020-09-29

申请号：US15721224

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： David A. Daycock ,  Purnima Narayanan ,  John Hopkins ,  Guoxing Duan ,  Barbara L. Casey ,  Christopher J. Larsen ,  Meng-Wei Kuo ,  Qian Tao

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L21/8234 ,  H01L27/11582 ,  H01L27/11556

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

公开(公告)号：US10217755B2

公开(公告)日：2019-02-26

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: G11C16/04 ,  H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US20180294272A1

公开(公告)日：2018-10-11

申请号：US15798352

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Darwin Fan ,  Sateesh Koka ,  Gordon Haller ,  John Hopkins ,  Shyam Surthi ,  Anish Khandekar

IPC: H01L27/11524 ,  H01L21/28 ,  H01L27/11556

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

公开(公告)号：US10096610B1

公开(公告)日：2018-10-09

申请号：US15721544

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： John Hopkins ,  Younghee Kim ,  Jie Li ,  Yu Yuwen ,  Ramey Abdelrahaman ,  Kunal Shrotri

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L29/10 ,  H01L29/788

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.

公开(公告)号：US20230065187A1

公开(公告)日：2023-03-02

申请号：US18047094

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： John Hopkins ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: Systems, apparatuses, and methods may provide for technology for forming extended air gaps for bitline contacts. For example, such technology patterns and etches a dielectric layer and a bitline layer to create bitline contacts in a memory die. An air gap dielectric layer is deposited to form an air gap between adjacent bitline contacts, and wherein the air gap has a height dimension that extends past a height dimension of the bitline contacts.

公开(公告)号：US20180286876A1

公开(公告)日：2018-10-04

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L27/11524 ,  H01L27/1157 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US09478643B2

公开(公告)日：2016-10-25

申请号：US14140215

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： John Hopkins ,  Fatma A. Simsek-Ege

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7889

Abstract: A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed between a first insulator layer and a second insulator layer, a floating gate material disposed between the first insulator layer and the second insulator layer and at least substantially aligned with the control gate material, the floating gate material including a metal region, and an interpoly dielectric (IPD) layer disposed between the control gate material and the floating gate material such that the IPD layer electrically isolates the control gate material from the floating gate material.

Abstract translation: 一种具有至少基本对准的浮动和控制门的存储器结构。 这种存储器结构可以包括设置在第一绝缘体层和第二绝缘体层之间的控制栅极材料，设置在第一绝缘体层和第二绝缘体层之间并至少基本上与控制栅极材料对准的浮栅材料，浮动栅极材料 包括金属区域的栅极材料和设置在控制栅极材料和浮置栅极材料之间的多晶硅间电介质（IPD）层，使得IPD层将控制栅极材料与浮动栅极材料电隔离。