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公开(公告)号：US20240362084A1
公开(公告)日：2024-10-31
申请号：US18677458
申请日：2024-05-29
Applicant: Intel Corporation
Inventor： STAV GURTOVOY , MATEUSZ MARIA PRZYBYLSKI , MICHAEL APODACA , MANJUNATH DS
CPC classification number: G06F9/52 , G06F9/4881 , G06F9/522 , G06T1/20
Abstract: An apparatus to facilitate thread synchronization is disclosed. The apparatus comprises one or more processors to execute a producer thread to generate a plurality of commands, execute a consumer thread to process the plurality of commands and synchronize the producer thread with the consumer thread, including updating a producer fence value upon generation of in-order commands, updating a consumer fence value upon processing of the in-order commands and performing a synchronization operation based on the consumer fence value, wherein the producer fence value and the consumer fence value each correspond to an order position of an in-order command.
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公开(公告)号：US20210327120A1
公开(公告)日：2021-10-21
申请号：US17308828
申请日：2021-05-05
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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3.发明申请公开(公告)号：US20200005516A1
公开(公告)日：2020-01-02
申请号：US16024821
申请日：2018-06-30
Applicant: Intel Corporation
Inventor： MICHAEL APODACA , ANKUR SHAH , BEN ASHBAUGH , BRANDON FLIFLET , HEMA NALLURI , PATTABHIRAMAN K , PETER DOYLE , JOSEPH KOSTON , JAMES VALERIO , MURALI RAMADOSS , ALTUG KOKER , ADITYA NAVALE , PRASOONKUMAR SURTI , BALAJI VEMBU
IPC: G06T15/00
Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
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公开(公告)号：US20200211272A1
公开(公告)日：2020-07-02
申请号：US16235517
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX , CARSON BROWNLEE , GABOR LIKTOR
Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.
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5.发明申请公开(公告)号：US20200045285A1
公开(公告)日：2020-02-06
申请号：US16050322
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： MAYURESH VARERKAR , STANLEY BARAN , MICHAEL APODACA , PRASOONKUMAR SURTI , ATSUO KUWAHARA , NARAYAN BISWAL , JILL BOYCE , YI-JEN CHIU , GOKCEN CILINGIR , BARNAN DAS , ATUL DIVEKAR , SRIKANTH POTLURI , NILESH SHAH , ARCHIE SHARMA
IPC: H04N13/111 , H04N19/597 , G06F3/01 , G06F9/38 , G06F15/18
Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
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Patent Agency Ranking
公开(公告)号：US20190066355A1
公开(公告)日：2019-02-28
申请号：US15692973
申请日：2017-08-31
Applicant: Intel Corporation
Inventor： TRAVIS T. SCHLUESSLER , MICHAEL APODACA , PENG GUO , WILLIAM B. DAVIDSON , GUEI-YUAN LUEH
Abstract: An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.
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公开(公告)号：US20180286009A1
公开(公告)日：2018-10-04
申请号：US15992642
申请日：2018-05-30
Applicant: Intel Corporation
Inventor： JEFFERY S. BOLES , HEMA C. NALLURI , BALAJI VEMBU , MICHAEL APODACA , ALTUG KOKER , LALIT K. SAPTARSHI
IPC: G06T1/20 , G06F3/06 , G06F12/0846 , G06T1/60 , G09G5/36
Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.
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公开(公告)号：US20230244609A1
公开(公告)日：2023-08-03
申请号：US18148749
申请日：2022-12-30
Applicant: Intel Corporation
Inventor： ZACK S. WATERS , TRAVIS SCHLUESSLER , MICHAEL APODACA , ANKUR SHAH
IPC: G06F12/0882 , G06F12/0837 , G06F12/1045 , G06F11/30 , G06F9/50 , G06F9/4401 , G06F9/54 , G06F12/06
CPC classification number: G06F12/0882 , G06F12/0837 , G06F12/1054 , G06F12/1063 , G06F11/3006 , G06F9/5016 , G06F9/4411 , G06F9/544 , G06F11/3037 , G06F12/0607
Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.
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公开(公告)号：US20210150770A1
公开(公告)日：2021-05-20
申请号：US17095544
申请日：2020-11-11
Applicant: Intel Corporation
Inventor： ABHISHEK R. APPU , PRASOONKUMAR SURTI , JILL BOYCE , SUBRAMANIAM MAIYURAN , MICHAEL APODACA , ADAM T. LAKE , JAMES HOLLAND , VASANTH RANGANATHAN , ALTUG KOKER , LIDONG XU , NIKOS KABURLASOS
Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.
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公开(公告)号：US20200211266A1
公开(公告)日：2020-07-02
申请号：US16236245
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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