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    THREE-DIMENSIONAL FLOATING BODY MEMORY
    1.
    发明申请
    THREE-DIMENSIONAL FLOATING BODY MEMORY 有权

    公开(公告)号：US20250008723A1

    公开(公告)日：2025-01-02

    申请号：US18341852

    申请日：2023-06-27

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Sagar Suthram

    IPC: H10B12/00 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

    Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.

    MEMORY ARRAYS WITH BACKSIDE COMPONENTS AND ANGLED TRANSISTORS
    3.
    发明公开
    MEMORY ARRAYS WITH BACKSIDE COMPONENTS AND ANGLED TRANSISTORS 审中-公开

    公开(公告)号：US20240008255A1

    公开(公告)日：2024-01-04

    申请号：US18325492

    申请日：2023-05-30

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy ,  Cory E. Weber ,  Rishabh Mehandru ,  Wilfred Gomes ,  Pushkar Sharad Ranade

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05 ,  H10B12/482

    Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

    FIELD-EFFECT TRANSISTOR WITH HYBRID SWITCHING MECHANISM
    8.
    发明公开
    FIELD-EFFECT TRANSISTOR WITH HYBRID SWITCHING MECHANISM 审中-公开

    公开(公告)号：US20230275151A1

    公开(公告)日：2023-08-31

    申请号：US17680365

    申请日：2022-02-25

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Anand S. Murthy ,  Tahir Ghani ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Sagar Suthram

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L21/823807

    Abstract: Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.

    STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
    9.
    发明申请
    STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE 有权

    公开(公告)号：US20250104760A1

    公开(公告)日：2025-03-27

    申请号：US18471382

    申请日：2023-09-21

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

    Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.

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