公开(公告)号：US20230305057A1

公开(公告)日：2023-09-28

申请号：US17701323

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Xianghong Tong ,  Martin Von Haartman ,  Zhiyong Ma ,  Jennifer J. Huening ,  Hyuk Ju Ryu ,  Christopher Morgan ,  Shuai Zhao ,  Ramune Nagisetty ,  Tuyen K. Tran ,  Wen-Hsien Chuang

IPC: G01R31/307 ,  G01R1/073

CPC classification number: G01R31/307 ,  G01R1/07342

Abstract: Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.

公开(公告)号：US20230317408A1

公开(公告)日：2023-10-05

申请号：US17711785

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Xianghong Tong ,  Martin Von Haartman ,  Wen-Hsien Chuang ,  Zhiyong Ma ,  Hyuk Ju Ryu ,  Prasoon Joshi ,  May Ling Oh ,  Jennifer Huening ,  Shuai Zhao ,  Charles Peterson ,  Ira Jewell ,  Hasan Faraby

IPC: H01J37/26 ,  H01J37/28 ,  H01J37/244

CPC classification number: H01J37/265 ,  H01J37/28 ,  H01J37/244 ,  H01J2237/2443 ,  H01J2237/2814 ,  H01J2237/2801 ,  H01J2237/221

Abstract: Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.

公开(公告)号：US11749560B2

公开(公告)日：2023-09-05

申请号：US16141522

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC: H01L21/768 ,  H01L23/532 ,  C25D3/58 ,  C23C18/48

CPC classification number: H01L21/76802 ,  C23C18/48 ,  C25D3/58 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53223 ,  H01L23/53238

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US20200098619A1

公开(公告)日：2020-03-26

申请号：US16141522

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC: H01L21/768 ,  H01L23/532 ,  C23C18/48 ,  C25D3/58

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US09123724B2

公开(公告)日：2015-09-01

申请号：US14134097

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Xianghong Tong ,  Zhanping Chen ,  Walid M. Hafez ,  Zhiyong Ma ,  Sarvesh H. Kulkarni ,  Kevin X. Zhang ,  Matthew B. Pedersen ,  Kevin D. Johnson

IPC: H01L27/11 ,  H01L29/04 ,  H01L21/02 ,  H01L23/58 ,  H01L23/525 ,  H01L27/02 ,  H01L27/112 ,  H01L27/06 ,  H01L21/44 ,  H01L29/861

CPC classification number: H01L23/5252 ,  H01L21/44 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Abstract translation: 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。