公开(公告)号：US20080200031A1

公开(公告)日：2008-08-21

申请号：US12007999

申请日：2008-01-18

申请人： Jang-hee Lee ,  Tae-ho Cha ,  Hae-sook Park ,  Gil-heyun Choi ,  Byung-hee Kim

发明人： Jang-hee Lee ,  Tae-ho Cha ,  Hae-sook Park ,  Gil-heyun Choi ,  Byung-hee Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/28061 ,  H01L29/4941 ,  H01L29/78

摘要： A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer.

摘要翻译： 根据示例实施例的形成半导体器件的栅电极的方法，其可以包括在半导体衬底上形成多晶硅膜。 可以通过多次重复单位周期在多晶硅膜上形成界面控制层。 单元循环可以包括形成界面金属膜并氮化界面金属膜的上表面部分以在界面金属膜的上表面部分上形成界面金属氮化物膜。 可以在界面控制层上形成布线金属膜。

公开(公告)号：US20060292784A1

公开(公告)日：2006-12-28

申请号：US11424995

申请日：2006-06-19

申请人： Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

发明人： Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

IPC分类号： H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/321 ,  H01L21/823437 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is annealed and the annealed semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is plasma oxidized.

摘要翻译： 形成集成电路器件的方法可以包括在半导体衬底的外围电路区域中的半导体衬底的存储单元区域和多个高压晶体管栅极中形成多个堆叠的单元栅极。 包括多个堆叠的单元栅极和多个高压晶体管栅极的半导体基板被退火，并且包括多个堆叠的单元栅极和多个高压晶体管栅极的退火的半导体衬底被等离子体氧化。

公开(公告)号：US20090189229A1

公开(公告)日：2009-07-30

申请号：US12315436

申请日：2008-12-03

申请人： Jong-min Baek ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Tae-ho Cha ,  Hee-sook Park ,  Byung-hak Lee ,  Jae-hwa Park

发明人： Jong-min Baek ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Tae-ho Cha ,  Hee-sook Park ,  Byung-hak Lee ,  Jae-hwa Park

IPC分类号： H01L21/283 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L21/28061 ,  H01L29/4933

摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

摘要翻译： 提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。 半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

公开(公告)号：US08466052B2

公开(公告)日：2013-06-18

申请号：US12704358

申请日：2010-02-11

申请人： Jong-min Baek ,  Hee-sook Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Byung-hak Lee ,  Tae-ho Cha ,  Jae-hwa Park ,  Su-kyoung Kim

发明人： Jong-min Baek ,  Hee-sook Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Byung-hak Lee ,  Tae-ho Cha ,  Jae-hwa Park ,  Su-kyoung Kim

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213

CPC分类号： H01L27/10891

摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在 沟。 可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

公开(公告)号：US07781849B2

公开(公告)日：2010-08-24

申请号：US12315436

申请日：2008-12-03

申请人： Jong-min Baek ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Tae-ho Cha ,  Hee-sook Park ,  Byung-hak Lee ,  Jae-hwa Park

发明人： Jong-min Baek ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Tae-ho Cha ,  Hee-sook Park ,  Byung-hak Lee ,  Jae-hwa Park

IPC分类号： H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/49

CPC分类号： H01L21/28061 ,  H01L29/4933

摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

摘要翻译： 提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。 半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

公开(公告)号：US20100210105A1

公开(公告)日：2010-08-19

申请号：US12704358

申请日：2010-02-11

申请人： Jong-min Baek ,  Hee-sook Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Byung-hak Lee ,  Tae-ho Cha ,  Jae-hwa Park ,  Su-kyoung Kim

发明人： Jong-min Baek ,  Hee-sook Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Byung-hak Lee ,  Tae-ho Cha ,  Jae-hwa Park ,  Su-kyoung Kim

IPC分类号： H01L21/768

CPC分类号： H01L27/10891

摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在 沟。 可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

公开(公告)号：US07518214B2

公开(公告)日：2009-04-14

申请号：US11586610

申请日：2006-10-26

申请人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

发明人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC分类号： H01L29/00

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

公开(公告)号：US20070099365A1

公开(公告)日：2007-05-03

申请号：US11586610

申请日：2006-10-26

申请人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

发明人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC分类号： H01L21/8234

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。