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公开(公告)号：US5846871A
公开(公告)日：1998-12-08
申请号：US918394
申请日：1997-08-26
申请人： Jean Ling Lee , Yi Ma , Sailesh Mansinh Merchant
发明人： Jean Ling Lee , Yi Ma , Sailesh Mansinh Merchant
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L21/283
CPC分类号： H01L21/823835 , H01L21/28061
摘要： Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.
摘要翻译： 例如通过穿过上覆硅化物的交叉扩散，n + / p +门的不期望的反向掺杂被多晶硅栅极和覆盖的硅化物之间插入氮化钛和钛，钨或钽层。
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公开(公告)号：US06320238B1
公开(公告)日：2001-11-20
申请号：US09339895
申请日：1999-06-25
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
摘要翻译： 本发明涉及一种具有设置在其上设置有栅电极的基板上的电介质材料层的栅极堆叠结构。 在一个示例性实施例中，电介质材料层具有2.2nm或更小的等效电气厚度，并且包括除二氧化硅之外的至少一个层。 此外，本发明的电介质材料层能够进行器件定标，并且与常规栅极电介质相比提供（1）降低的漏电流和改善的隧穿电压; 和（2）当专门用作栅极电介质时，避免超薄二氧化硅的危险。
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公开(公告)号：US5981403A
公开(公告)日：1999-11-09
申请号：US977319
申请日：1997-11-24
IPC分类号： H01L21/28 , H01L21/314 , H01L21/318 , H01L21/32 , H01L21/762 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/3145 , H01L21/3185 , H01L21/32 , H01L21/76202 , H01L29/513 , H01L29/518
摘要： A semiconductor device process for forming a multilayered nitride structure. The nitride is used as either isolation or as part of a dielectric structure. The deposition rate for the nitride is varied to form a multilayered structure with stress accommodation at the interface between sub-layers in the multilayer structure. In addition, the sub-layered structure reduces pin-holes and microcracks in the nitride film and improves the overall uniformity in thickness of the final nitride film.
摘要翻译： 一种用于形成多层氮化物结构的半导体器件工艺。 氮化物被用作隔离或作为电介质结构的一部分。 改变氮化物的沉积速率以形成在多层结构中的子层之间的界面处具有应力调节的多层结构。 此外，亚层结构减少氮化物膜中的针孔和微裂纹，并且改善最终氮化物膜的厚度的总体均匀性。
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公开(公告)号：US06147388A
公开(公告)日：2000-11-14
申请号：US977318
申请日：1997-11-24
申请人： Yi Ma , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy
发明人： Yi Ma , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy
IPC分类号： H01L29/78 , H01L21/28 , H01L21/324 , H01L21/8238 , H01L27/092 , H01L29/43 , H01L29/49 , H01L21/283 , H01L21/265
CPC分类号： H01L21/324 , H01L21/28061 , H01L29/4925 , H01L29/4941
摘要： A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.
摘要翻译： CMOS栅极结构包括多层多晶硅结构和沉积的硅化物层，其间形成氮化硅化物阻挡层。 多层多晶硅将具有相对较大的晶粒尺寸和均匀的结构。 将沉积的硅化物层退火以模拟多晶硅晶粒尺寸和结构。 定制的晶粒结构与中间阻挡层的组合导致栅极结构，其基本上不渗透随后的掺杂剂扩散。
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公开(公告)号：US06686662B2
公开(公告)日：2004-02-03
申请号：US10153231
申请日：2002-05-21
IPC分类号： H01L2352
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A barrier layer for a semiconductor device metallization component provides a silicon nitride film formed in a component recess and a refractory metal film formed over the silicon nitride film. The device component includes a dielectric material and a recess formed in the dielectric. The surface of the dielectric material within the recess is exposed to nitrogen under controlled parameters. A section of the dielectric material adjacent an interior of the recess is converted to silicon nitride. The refractory metal is then conformed deposited along the recess sidewalls. A seed layer is then deposited over the refractory metal film, and a conductive metal is then deposited within the recess. The device is then polished to remove excess metal outside the recess and planarize the device.
摘要翻译： 用于半导体器件金属化部件的阻挡层提供形成在氮化硅膜上的部件凹部和难熔金属膜中的氮化硅膜。 器件部件包括介电材料和形成在电介质中的凹部。 凹陷内的电介质材料的表面在受控参数下暴露于氮气。 与凹陷内部相邻的电介质材料的一部分被转换成氮化硅。随后，难熔金属沿凹槽侧壁沉积。 然后将种子层沉积在难熔金属膜上，然后在凹槽内沉积导电金属。 然后将该装置抛光以除去凹部外部的多余金属并使装置平坦化。
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公开(公告)号：US06585830B2
公开(公告)日：2003-07-01
申请号：US09727326
申请日：2000-11-30
IPC分类号： B08B500
CPC分类号： C23C16/4405
摘要： An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.
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公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译： 本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽 以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。
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公开(公告)号：US06331484B1
公开(公告)日：2001-12-18
申请号：US09519193
申请日：2000-03-06
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/76807 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.
摘要翻译： 用于与诸如铜的互连膜一起使用的钛 - 钽阻挡层膜及其形成方法提供了与其形成的界面相邻的富钛/钽缺陷部分，其与介电膜和相对富钽/钛 与其形成的界面相邻的缺陷部分与在阻挡层膜上形成的导电互连膜形成。 富钛/钽缺陷部分对电介质膜提供良好的粘附性，并且富钽/钛缺陷部分与互连膜形成异质外延界面并抑制金属间化合物的形成。 可以使用包括PVD，CVD，使用均匀组合物的溅射靶的溅射沉积以及使用多个溅射靶的溅射沉积的各种技术来形成具有从顶部到底部的组成梯度的单个钛 - 钽膜。 复合钛 - 钽薄膜由两个单独形成的薄膜组成。
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9.发明授权Method of forming capacitor having the lower metal electrode for preventing undesired defects at the surface of the metal plug 有权形成具有下金属电极的电容器的方法，用于防止金属插头表面的不期望的缺陷公开(公告)号：US06323044B1
公开(公告)日：2001-11-27
申请号：US09408299
申请日：1999-09-29
IPC分类号： H01L2100
CPC分类号： H01L28/60 , H01L21/28568
摘要： An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.
摘要翻译： 集成电路电容器包括邻近衬底的电介质层中的金属插塞。 金属插塞在其最上表面部分具有至少一个形貌缺陷。 下部金属电极覆盖在电介质层和金属插头上。 下部金属电极以堆叠关系包括金属层，下部金属氮化物层，铝层和上部金属氮化物层。 电容器电介质层覆盖在下金属电极上，并且上金属电极覆盖在电容器介电层上。 这种结构的优点是，下金属电极的金属层堆叠将防止在金属插塞表面的不期望的缺陷不利地影响器件的可靠性或制造成品率。
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公开(公告)号：US06319837B1
公开(公告)日：2001-11-20
申请号：US09606833
申请日：2000-06-29
IPC分类号： H01L2100
CPC分类号： H01L21/7684
摘要： The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
摘要翻译： 本发明包括一种用于减少集成电路互连的凹陷的方法，包括以下步骤：在衬底上的镶嵌特征之上提供过量的互连材料，并平坦化衬底和互连材料以获得衬底中的互连。
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