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87 条记录 (耗时 0.041 秒)

    Gate structure for integrated circuit fabrication
    1.
    发明授权
    Gate structure for integrated circuit fabrication 有权
    集成电路制造的门结构

    公开(公告)号：US06320238B1

    公开(公告)日：2001-11-20

    申请号：US09339895

    申请日：1999-06-25

    申请人： Isik C. Kizilyalli ,  Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

    发明人： Isik C. Kizilyalli ,  Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

    IPC分类号： H01L2976

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

    摘要： The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.

    摘要翻译： 本发明涉及一种具有设置在其上设置有栅电极的基板上的电介质材料层的栅极堆叠结构。 在一个示例性实施例中，电介质材料层具有2.2nm或更小的等效电气厚度，并且包括除二氧化硅之外的至少一个层。 此外，本发明的电介质材料层能够进行器件定标，并且与常规栅极电介质相比提供（1）降低的漏电流和改善的隧穿电压; 和（2）当专门用作栅极电介质时，避免超薄二氧化硅的危险。

    Compound, high-K, gate and capacitor insulator layer
    4.
    发明授权
    Compound, high-K, gate and capacitor insulator layer 失效
    复合，高K，栅极和电容绝缘层

    公开(公告)号：US06548854B1

    公开(公告)日：2003-04-15

    申请号：US08995435

    申请日：1997-12-22

    申请人： Isik C. Kizilyalli ,  Yi Ma ,  Pradip Kumar Roy

    发明人： Isik C. Kizilyalli ,  Yi Ma ,  Pradip Kumar Roy

    IPC分类号： H01L2976

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

    摘要： A gate or capacitor insulator structure using a first grown oxide layer, a high-k dielectric material on the grown oxide layer, and a deposited oxide layer on the high-k dielectric material. The deposited oxide layer is preferably a densified deposited oxide layer. A conducting layer, such as a gate or capacitor plate, may overlay the densified oxide layer.

    摘要翻译： 使用第一生长氧化物层，生长的氧化物层上的高k电介质材料和高k电介质材料上的沉积氧化物层的栅极或电容器绝缘体结构。 沉积的氧化物层优选是致密化的沉积氧化物层。 诸如栅极或电容器板的导电层可以覆盖致密的氧化物层。

    Use of SiD.sub.4 for deposition of ultra thin and controllable oxides
    6.
    发明授权
    Use of SiD.sub.4 for deposition of ultra thin and controllable oxides 失效
    使用SiD4沉积超薄和可控的氧化物

    公开(公告)号：US6025280A

    公开(公告)日：2000-02-15

    申请号：US848109

    申请日：1997-04-28

    申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

    发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

    IPC分类号： C23C16/40 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

    摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

    摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压，跨导），迁移率降低和耐热性降低的散射 载体和福勒 - 诺德海姆压力。

    System and method for forming a uniform thin gate oxide layer
    7.
    发明授权
    System and method for forming a uniform thin gate oxide layer 有权
    用于形成均匀的薄栅氧化层的系统和方法

    公开(公告)号：US06281138B1

    公开(公告)日：2001-08-28

    申请号：US09338939

    申请日：1999-06-24

    申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

    发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

    摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

    摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在存在应力容纳的情况下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。

    Method of making a dielectric for an integrated circuit
    9.
    发明授权
    Method of making a dielectric for an integrated circuit 失效
    制造集成电路电介质的方法

    公开(公告)号：US5960302A

    公开(公告)日：1999-09-28

    申请号：US775790

    申请日：1996-12-31

    申请人： Yi Ma ,  Pradip Kumar Roy ,  Kevin Yun-Kang Wu

    发明人： Yi Ma ,  Pradip Kumar Roy ,  Kevin Yun-Kang Wu

    IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/3205

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

    摘要： A composite 3-layer gate dielectric is disclosed. The upper and lower layers have a concentration of nitrogen atoms, while the middle layer has very few nitrogen atoms. The presence of the nitrogen atoms in the top sublayers provides resistance to boron diffusion from the top conductive layer and plasma damage during polysilicon gate stack formation and the presence of nitrogen in the bottom sublayer near the silicon-dielectric interface improves wearout, endurance, resistance to current stress and electron traps.

    摘要翻译： 公开了复合三层栅极电介质。 上层和下层具有氮原子的浓度，而中间层具有非常少的氮原子。 顶层子层中氮原子的存在提供了对顶部导电层的硼扩散的阻力和在多晶硅栅叠层形成期间的等离子体损伤，并且在硅 - 介电界面附近的底层子层中存在氮，从而改善了耐磨性，耐久性 电流应力和电子阱。