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公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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2.发明授权公开(公告)号：US08909690B2
公开(公告)日：2014-12-09
申请号：US13324025
申请日：2011-12-13
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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公开(公告)号：US20130151577A1
公开(公告)日：2013-06-13
申请号：US13324025
申请日：2011-12-13
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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4.发明授权公开(公告)号：US08984041B2
公开(公告)日：2015-03-17
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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公开(公告)号：US07587559B2
公开(公告)日：2009-09-08
申请号：US11463743
申请日：2006-08-10
IPC分类号： G06F12/00
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。
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6.发明申请SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT 失效基于多通道占空比的存储器电源管理的同步指令脉宽调制公开(公告)号：US20130151867A1
公开(公告)日：2013-06-13
申请号：US13314379
申请日：2011-12-08
CPC分类号： G06F3/0644 , G06F1/32 , G06F1/3206 , G06F1/3275 , G06F13/16 , G11C5/147 , G11C11/4074 , Y02D10/14
摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.
摘要翻译： 在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。 同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。 响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。 响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。 响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。 具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。
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公开(公告)号：US20080040563A1
公开(公告)日：2008-02-14
申请号：US11463743
申请日：2006-08-10
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。
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公开(公告)号：US20140082272A1
公开(公告)日：2014-03-20
申请号：US13781519
申请日：2013-02-28
IPC分类号： G11C11/406 , G06F13/16
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.
摘要翻译： 一种用于控制动态随机存取存储器中的存储器刷新操作的方法。 该方法包括确定第一存储器等级的延迟存储器刷新操作的计数。 响应于接近高优先级阈值的计数，发出用于第一存储器级的早期高优先级刷新通知，其指示在第一存储器级执行高优先级存储器刷新操作的预定时间。 响应于早期高优先级刷新通知，动态地修改读取重新排序队列的行为，以便对至少一个针对第一存储器等级的读取命令给出优先级调度，并且在所述至少一个读取命令中执行一个或多个读取命令 根据优先级调度的第一内存等级。 优先级调度在刷新操作以第一存储器等级开始之前从重新排序队列中移除这些命令。
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9.发明申请公开(公告)号：US20090327615A1
公开(公告)日：2009-12-31
申请号：US12105360
申请日：2008-04-18
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译： 访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，可以从第一数据请求中提取第一地址和范围预测器。 可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。 可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为 必要。
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10.发明授权Access speculation predictor implemented via idle command processing resources 失效通过空闲命令处理资源实现访问推测预测器公开(公告)号：US08131974B2
公开(公告)日：2012-03-06
申请号：US12105427
申请日：2008-04-18
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/507 , G06F2212/6022 , G06F2212/6024 , Y02D10/13
摘要： An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.
摘要翻译： 提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。 访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。 特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。 可以选择其存储区域包括第一地址的FSM。 可以从所选择的FSM获得用于存储器区域的历史信息。 历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。
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