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公开(公告)号：US08954828B2
公开(公告)日：2015-02-10
申请号：US13841923
申请日：2013-03-15
发明人： Osamu Torii , Shinichi Kanno , Ryo Yamaki
CPC分类号： H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/2906
摘要： According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i−1)-th parities.
摘要翻译： 根据实施例，存储器控制器包括：编码单元，用于对用户数据执行纠错编码处理以产生第一至第n个奇偶校验，并对第一至第n个奇偶校验中的每一个进行纠错编码处理，以产生 第一到第n外部平等; 以及解码单元，其使用用户数据，第一至第n个奇偶校验和第一至第n个外部奇偶校验来执行纠错解码处理。 基于用于生成第一至第（i-1）个奇偶校验的生成多项式来选择用于生成第i个奇偶校验的生成多项式。
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公开(公告)号：US09548107B1
公开(公告)日：2017-01-17
申请号：US14963482
申请日：2015-12-09
发明人： Naoko Kifune , Masanobu Shirakawa , Ryo Yamaki , Osamu Torii
CPC分类号： G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/28 , G11C2211/5642 , G11C2211/5648
摘要： A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.
摘要翻译： 半导体存储器件包括被配置为根据阈值保持4位数据的存储器单元。 通过使用第一至第三读取电平读取操作来建立4位数据的第一位。 通过使用第四到第七读取电平的读取操作来建立与第一位不同的第二位。 通过使用第八到第十一读取电平的读取操作来建立与第一和第二位不同的第三位。 通过使用第十二至第十五读取电平的读取操作来建立与第一至第三位不同的第四位。
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公开(公告)号：US09424126B2
公开(公告)日：2016-08-23
申请号：US14205800
申请日：2014-03-12
发明人： Ryo Yamaki , Naomi Takeda
CPC分类号： G06F11/1012
摘要： According to one embodiment, a memory controller according to the embodiments includes an encoder that sequentially calculates parity based on data; a parity buffer that stores completed parity and intermediate parity based on data less than a predetermined size; a write processing unit that writes data and completed parity on a non-volatile memory; a decoder; and a controller that performs a decoding process based on the data read from the non-volatile memory and the intermediate parity in the parity buffer, when receiving a read request to inputted data in a stage in which the a number of inputted data to the encoder is less than the predetermined size.
摘要翻译： 根据一个实施例，根据实施例的存储器控制器包括基于数据顺序地计算奇偶校验的编码器; 奇偶校验缓冲器，其基于小于预定大小的数据存储完成的奇偶校验和中间奇偶校验; 写入处理单元，其将数据和完成的奇偶校验写入非易失性存储器; 解码器 以及控制器，当在输入到编码器的输入数据的数量级中接收到对输入数据的读取请求时，基于从非易失性存储器读取的数据和奇偶校验缓冲器中的中间奇偶校验来执行解码处理 小于预定尺寸。
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公开(公告)号：US20140068378A1
公开(公告)日：2014-03-06
申请号：US13772659
申请日：2013-02-21
发明人： Kenichiro YOSHII , Naoaki Kokubun , Naoto Oshiyama , Ryo Yamaki , Ikuo Magaki , Kenta Yasufuku , Akira Yamaga
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , H03M13/152 , H03M13/1525 , H03M13/154
摘要： According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.
摘要翻译： 根据实施例，半导体存储装置包括存储器，产生奇偶校验的编码单元和包括校正子计算单元，错误位置多项式计算单元和错误搜索和校正单元的解码单元，并且执行 基于数据的错误纠正处理和从存储器读取的奇偶校验。 在执行压缩处理时，当通过错误位置多项式获取的错误位的数量等于或小于基于有效数据的第一阈值时，不执行错误搜索和校正单元的处理。
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公开(公告)号：US20160246603A1
公开(公告)日：2016-08-25
申请号：US14743061
申请日：2015-06-18
发明人： Daiki WATANABE , Daisuke Fujiwara , Ryo Yamaki
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/3004 , G06F11/1012 , G11C16/26 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/3707 , H03M13/451 , H03M13/458
摘要： According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.
摘要翻译： 根据一个实施例，存储器控制器包括被配置为执行近似最大似然解码的解码器，所述解码器包括：初始值生成单元，被配置为基于从非易失性存储器读取的接收字来计算第一数据; 存储单元，被配置为存储所述第一数据和预定数量的第二数据; 更新单元，被配置为通过使用存储的预定数量的第二数据来计算新的第二数据，并更新存储单元; 算术单元，被配置为输出第一数据和最新的第二数据的相加结果作为解码字信息; 以及选择单元，被配置为基于多个解码字信息来选择具有最大似然性的解码字。
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公开(公告)号：US09424929B1
公开(公告)日：2016-08-23
申请号：US14848829
申请日：2015-09-09
发明人： Ryo Yamaki , Masanobu Shirakawa
CPC分类号： G11C16/08 , G11C7/1006 , G11C16/10 , G11C16/26 , G11C16/32
摘要： According to an embodiment, a memory system includes: a nonvolatile memory to which data in the unit of I/O data of the first number of bits are capable of being input in parallel, and from which data in the unit of I/O data are capable of being output in parallel; a memory interface; an encoding unit configured to generate the second number of codewords; a decoding unit configured to decode a received word read from the nonvolatile memory; and a control unit configured to link an I/O number to the number of the codeword, inputs, to the encoder, each of the codewords of the data to be input to the nonvolatile memory as the data about the position of the bit having the I/O number corresponding to the codeword, reads the second number of received words from the nonvolatile memory to decode the received words, and, when there is a received word that fails to be decoded, reads the received words again after changing the reading voltage, and decodes the received word.
摘要翻译： 根据实施例，存储器系统包括：非易失性存储器，能够并行地输入第一位数的I / O数据单元中的数据，以I / O数据为单位的数据 能够并行输出; 存储器接口; 编码单元，被配置为生成所述第二数量的码字; 解码单元，被配置为对从非易失性存储器读取的接收字进行解码; 以及控制单元，被配置为将I / O号与所述码字的数量相关联，将要输入到所述非易失性存储器的数据的每个码字输入到所述编码器，作为关于所述位的所述位的数据 对应于码字的I / O号，从非易失性存储器中读出第二数量的接收字来解码所接收的字，并且当存在不能解码的接收字时，在更改读取电压之后再次读取接收到的字 ，并对接收到的字进行解码。
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7.发明授权Memory controller, semiconductor storage device, and memory control method for error correction using Chien search 有权存储器控制器，半导体存储器件和使用Chien搜索进行纠错的存储器控制方法公开(公告)号：US08924828B2
公开(公告)日：2014-12-30
申请号：US13757976
申请日：2013-02-04
发明人： Naoaki Kokubun , Ryo Yamaki
CPC分类号： H03M13/159 , H03M13/152 , H03M13/1545 , H03M13/6561
摘要： According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a Chien search unit, wherein the Chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.
摘要翻译： 根据一个实施例，一种存储器控制器，包括：校正子计算单元，其基于具有校正t位的能力的代码字，误差定位多项式计算单元和Chien搜索单元来计算校正子，其中所述Chien搜索单元包括根 移位块，其移动所有根，划分块，其将来自根移位块的输出除以小于t的预定多项式，以及将元素替换为余数多项式以检查它们是否为根的替换块 ，并且其中所述预定多项式具有至少一个根，该值与所述替代元素中的一个相同。
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公开(公告)号：US08879349B2
公开(公告)日：2014-11-04
申请号：US13960186
申请日：2013-08-06
发明人： Kenichiro Yoshii , Ikuo Magaki , Naoto Oshiyama , Tokumasa Hara , Akira Yamaga , Ryo Yamaki , Kenta Yasufuku , Naomi Takeda , Yu Nakanishi , Arata Miyamoto , Naoaki Kokubun , Daisuke Iwai
IPC分类号： G11C5/14
摘要： A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
摘要翻译： 根据实施例的存储装置包括第一和第二非易失性半导体存储器。 此外，存储设备包括控制第一非易失性存储器以使第一非易失性存储器执行处理的第一控制器。 此外，存储设备包括控制第二非易失性存储器以使第二非易失性存储器执行处理的第二控制器。 存储装置还包括连接到第一控制器和第二控制器的信号线，通过该信号线在第一控制器和第二控制器之间传送令牌。 第一控制器能够在保持令牌的同时控制第一非易失性存储器，并且第二控制器能够在保持令牌的同时控制第二非易失性存储器。
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公开(公告)号：US09600364B2
公开(公告)日：2017-03-21
申请号：US14832023
申请日：2015-08-21
发明人： Osamu Torii , Haruka Obata , Ryo Yamaki , Daiki Watanabe
CPC分类号： G06F11/1068 , G06F11/1012 , G11C11/5642 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/2909
摘要： According to an embodiment, a row decoder to perform row decoding by using, as row soft input information, a row received word read as soft determination information from a non-volatile memory and to calculate row extrinsic information and a column decoder to perform column decoding by using column soft input information, which is a result of adding of the row extrinsic information to a column received word read as soft determination information from the non-volatile memory, and to calculate column extrinsic information are included. The row decoder includes a first decoder for first decoding, a second decoder for second decoding a decoding method of which is different from that of the first decoding, and a selection unit to select a decoded result based on accuracy of a decoded result of the first decoding and that of a decoded result of the second decoding and to calculate the row extrinsic information.
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公开(公告)号：US09588772B2
公开(公告)日：2017-03-07
申请号：US14743061
申请日：2015-06-18
发明人： Daiki Watanabe , Daisuke Fujiwara , Ryo Yamaki
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/3004 , G06F11/1012 , G11C16/26 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/3707 , H03M13/451 , H03M13/458
摘要： According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.
摘要翻译： 根据一个实施例，存储器控制器包括被配置为执行近似最大似然解码的解码器，所述解码器包括：初始值生成单元，被配置为基于从非易失性存储器读取的接收字来计算第一数据; 存储单元，被配置为存储所述第一数据和预定数量的第二数据; 更新单元，被配置为通过使用存储的预定数量的第二数据来计算新的第二数据，并更新存储单元; 算术单元，被配置为输出第一数据和最新的第二数据的相加结果作为解码字信息; 以及选择单元，被配置为基于多个解码字信息来选择具有最大似然性的解码字。
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