-
公开(公告)号：US09721666B2
公开(公告)日：2017-08-01
申请号：US15174527
申请日：2016-06-06
发明人： Masanobu Shirakawa , Kenta Yasufuku , Akira Yamaga
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/34 , G11C16/3427 , G11C16/3459 , G11C2211/5641
摘要： A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
-
公开(公告)号：US20140068378A1
公开(公告)日：2014-03-06
申请号：US13772659
申请日：2013-02-21
发明人： Kenichiro YOSHII , Naoaki Kokubun , Naoto Oshiyama , Ryo Yamaki , Ikuo Magaki , Kenta Yasufuku , Akira Yamaga
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , H03M13/152 , H03M13/1525 , H03M13/154
摘要： According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.
摘要翻译： 根据实施例，半导体存储装置包括存储器，产生奇偶校验的编码单元和包括校正子计算单元，错误位置多项式计算单元和错误搜索和校正单元的解码单元，并且执行 基于数据的错误纠正处理和从存储器读取的奇偶校验。 在执行压缩处理时，当通过错误位置多项式获取的错误位的数量等于或小于基于有效数据的第一阈值时，不执行错误搜索和校正单元的处理。
-
公开(公告)号：US09003269B2
公开(公告)日：2015-04-07
申请号：US13837950
申请日：2013-03-15
发明人： Naoto Oshiyama , Ryo Yamaki , Kenta Yasufuku , Naoaki Kokubun
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/154 , H03M13/1545 , H03M13/2906 , H03M13/2927 , H03M13/6502 , H03M13/6561
摘要： According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.
摘要翻译： 根据一个实施例，存储器控制器的解码器包括：校正子计算单元，被配置为基于从存储器读取的代码字来计算校正子; 错误定位器多项式生成单元，被配置为基于所述校正子生成错误定位器多项式，并且基于所生成的误差定位器多项式来获得多个误差; 以及误差位置计算单元，被配置为基于所述误差定位器多项式来计算误差位置，其中当所述误差数量不小于可校正的最大位数时，所述错误位置计算单元的处理不被执行 由误差定位器多项式生成单元。
-
公开(公告)号：US09081711B2
公开(公告)日：2015-07-14
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
-
公开(公告)号：US08879349B2
公开(公告)日：2014-11-04
申请号：US13960186
申请日：2013-08-06
发明人： Kenichiro Yoshii , Ikuo Magaki , Naoto Oshiyama , Tokumasa Hara , Akira Yamaga , Ryo Yamaki , Kenta Yasufuku , Naomi Takeda , Yu Nakanishi , Arata Miyamoto , Naoaki Kokubun , Daisuke Iwai
IPC分类号： G11C5/14
摘要： A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
摘要翻译： 根据实施例的存储装置包括第一和第二非易失性半导体存储器。 此外，存储设备包括控制第一非易失性存储器以使第一非易失性存储器执行处理的第一控制器。 此外，存储设备包括控制第二非易失性存储器以使第二非易失性存储器执行处理的第二控制器。 存储装置还包括连接到第一控制器和第二控制器的信号线，通过该信号线在第一控制器和第二控制器之间传送令牌。 第一控制器能够在保持令牌的同时控制第一非易失性存储器，并且第二控制器能够在保持令牌的同时控制第二非易失性存储器。
-
公开(公告)号：US20140164702A1
公开(公告)日：2014-06-12
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
-
公开(公告)号：US09003261B2
公开(公告)日：2015-04-07
申请号：US14017246
申请日：2013-09-03
发明人： Ikuo Magaki , Naoto Oshiyama , Kenichiro Yoshii , Kosuke Hatsuda , Shirou Fujita , Tokumasa Hara , Kohei Oikawa , Kenta Yasufuku
CPC分类号： G06F11/1008 , G06F11/1012
摘要： A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
摘要翻译： 存储器系统包括第一非易失性存储器，具有比第一非易失性存储器更长的访问延迟的第二非易失性存储器，第一纠错单元，第二纠错单元和接口。 第一非易失性存储器存储为第一数据生成的第一数据和第一纠错码。 第二非易失性存储器存储对于具有比第一纠错码更高的校正能力的第一数据产生的第二纠错码。 第一纠错单元通过使用第一纠错码对第一数据进行纠错。 第二纠错单元通过使用第二纠错码对第一数据进行纠错。 接口将纠错后的第一个数据发送给主机。
-
公开(公告)号：US20140068376A1
公开(公告)日：2014-03-06
申请号：US13837950
申请日：2013-03-15
发明人： Naoto OSHIYAMA , Ryo Yamaki , Kenta Yasufuku , Naoaki Kokubun
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/154 , H03M13/1545 , H03M13/2906 , H03M13/2927 , H03M13/6502 , H03M13/6561
摘要： According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.
摘要翻译： 根据一个实施例，存储器控制器的解码器包括：校正子计算单元，被配置为基于从存储器读取的代码字来计算校正子; 错误定位器多项式生成单元，被配置为基于所述校正子生成错误定位器多项式，并且基于所生成的误差定位器多项式来获得多个误差; 以及误差位置计算单元，被配置为基于所述误差定位器多项式来计算误差位置，其中当所述误差数量不小于可校正的最大位数时，所述错误位置计算单元的处理不被执行 由误差定位器多项式生成单元。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.019 秒)
