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1.发明授权Semiconductor memory device including strings including memory cell transistors 有权半导体存储器件包括包含存储单元晶体管的串公开(公告)号：US09431112B2
公开(公告)日：2016-08-30
申请号：US14200641
申请日：2014-03-07
发明人： Hiroshi Sukegawa , Ikuo Magaki , Tokumasa Hara , Shirou Fujita
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/3418 , H01L27/11582
摘要： A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
摘要翻译： 控制器控制包括第一和第二串的存储器。 第一和第二个字符串分别配置第一和第二个字符串组。 在每个串组中，从每个串组成的一组存储单元晶体管构成单元。 控制器被配置为：在第一串组中顺序写入串行耦合的存储单元晶体管分别属于的第一单元的数据; 在第二串组中顺序地写入串行耦合的存储单元晶体管分别属于的第一单元的数据; 并且顺序地在第一串组中以串行耦合的存储单元晶体管分别属于的第二单元的数据。
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公开(公告)号：US20170075623A1
公开(公告)日：2017-03-16
申请号：US15054333
申请日：2016-02-26
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/0685 , G06F12/0246 , G06F12/1009 , G06F2212/1032 , G06F2212/7201
摘要： According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.
摘要翻译： 根据一个实施例，存储器控制器包括第一易失性存储器，第二易失性存储器和控制器。 第一易失性存储器临时存储从外部获取的数据。 控制器将从第一易失性存储器传送的临时存储的数据控制到非易失性存储器，将传送的数据的对应信息存储在第二易失性存储器中的非易失性存储器中，并且更新存储在非易失性存储器中的对应信息， 基于存储在第二易失性存储器中的对应信息，在数据传送之后通过使用第一易失性存储器作为工作区域。 对应信息表示数据的逻辑地址和物理地址之间的关联。
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公开(公告)号：US20140068378A1
公开(公告)日：2014-03-06
申请号：US13772659
申请日：2013-02-21
发明人： Kenichiro YOSHII , Naoaki Kokubun , Naoto Oshiyama , Ryo Yamaki , Ikuo Magaki , Kenta Yasufuku , Akira Yamaga
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , H03M13/152 , H03M13/1525 , H03M13/154
摘要： According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.
摘要翻译： 根据实施例，半导体存储装置包括存储器，产生奇偶校验的编码单元和包括校正子计算单元，错误位置多项式计算单元和错误搜索和校正单元的解码单元，并且执行 基于数据的错误纠正处理和从存储器读取的奇偶校验。 在执行压缩处理时，当通过错误位置多项式获取的错误位的数量等于或小于基于有效数据的第一阈值时，不执行错误搜索和校正单元的处理。
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公开(公告)号：US20170199705A1
公开(公告)日：2017-07-13
申请号：US15230857
申请日：2016-08-08
发明人： Hiroshi SUKEGAWA , Ikuo Magaki , Tokumasa Hara , Shirou Fujita
IPC分类号： G06F3/06
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/3418 , H01L27/11582
摘要： A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
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公开(公告)号：US20150206590A1
公开(公告)日：2015-07-23
申请号：US14463835
申请日：2014-08-20
发明人： Haruka SAKUMA , Yoshiaki Fukuzumi , Hideaki Aochi , Hiroshi Sukegawa , Tokumasa Hara , Hiroshi Yao , Shirou Fujita , Ikuo Magaki , Kiwamu Sakuma , Masumi Saitoh
CPC分类号： G11C16/14 , G11C8/14 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3495 , H01L27/11573 , H01L27/11582
摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group.
摘要翻译： 根据一个实施例，存储器系统包括非易失性半导体存储器件和控制器。 该系统包括包括多个存储单元的非易失性半导体存储器件; 并且所述控制器被配置为控制对所述非易失性半导体存储器件的读取操作或写入操作的读取操作，写入操作和使用频率中的一个，并且被配置为改变对属于第一组存储器的存储器单元的控制 并且改变属于属于第一组的存储单元的上侧或下侧的第二组的存储单元的控制。
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公开(公告)号：US20150036430A1
公开(公告)日：2015-02-05
申请号：US14200641
申请日：2014-03-07
发明人： Hiroshi Sukegawa , Ikuo Magaki , Tokumasa Hara , Shirou Fujita
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/3418 , H01L27/11582
摘要： A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
摘要翻译： 控制器控制包括第一和第二串的存储器。 第一和第二个字符串分别配置第一和第二个字符串组。 在每个串组中，从每个串组成的一组存储单元晶体管构成单元。 控制器被配置为：在第一串组中顺序写入串行耦合的存储单元晶体管分别属于的第一单元的数据; 在第二串组中顺序地写入串行耦合的存储单元晶体管分别属于的第一单元的数据; 并且顺序地在第一串组中以串行耦合的存储单元晶体管分别属于的第二单元的数据。
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公开(公告)号：US08879349B2
公开(公告)日：2014-11-04
申请号：US13960186
申请日：2013-08-06
发明人： Kenichiro Yoshii , Ikuo Magaki , Naoto Oshiyama , Tokumasa Hara , Akira Yamaga , Ryo Yamaki , Kenta Yasufuku , Naomi Takeda , Yu Nakanishi , Arata Miyamoto , Naoaki Kokubun , Daisuke Iwai
IPC分类号： G11C5/14
摘要： A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
摘要翻译： 根据实施例的存储装置包括第一和第二非易失性半导体存储器。 此外，存储设备包括控制第一非易失性存储器以使第一非易失性存储器执行处理的第一控制器。 此外，存储设备包括控制第二非易失性存储器以使第二非易失性存储器执行处理的第二控制器。 存储装置还包括连接到第一控制器和第二控制器的信号线，通过该信号线在第一控制器和第二控制器之间传送令牌。 第一控制器能够在保持令牌的同时控制第一非易失性存储器，并且第二控制器能够在保持令牌的同时控制第二非易失性存储器。
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公开(公告)号：US20160034221A1
公开(公告)日：2016-02-04
申请号：US14641099
申请日：2015-03-06
发明人： Tatsuya Zettsu , Katsuhiko Ueki , Yoshihisa Kojima , Hiroshi Yao , Kenichiro Yoshii , Ikuo Magaki
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0659 , G06F3/0679 , Y02D10/154
摘要： According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.
摘要翻译： 根据一个实施例，存储器系统设置有非易失性存储器，控制器，易失性存储器和地址转换表。 地址转换表包括高电平和多个低电平。 高电平指示记录低电平的非易失性存储器中的位置。 低电平表示记录数据的非易失性存储器中的位置。 控制器在易失性存储器的第一区域中保持地址转换表的高电平，并且基于从正常功率状态到低功率的转换来切断对易失性存储器的第二区域的电力供应 州。
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公开(公告)号：US09003261B2
公开(公告)日：2015-04-07
申请号：US14017246
申请日：2013-09-03
发明人： Ikuo Magaki , Naoto Oshiyama , Kenichiro Yoshii , Kosuke Hatsuda , Shirou Fujita , Tokumasa Hara , Kohei Oikawa , Kenta Yasufuku
CPC分类号： G06F11/1008 , G06F11/1012
摘要： A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
摘要翻译： 存储器系统包括第一非易失性存储器，具有比第一非易失性存储器更长的访问延迟的第二非易失性存储器，第一纠错单元，第二纠错单元和接口。 第一非易失性存储器存储为第一数据生成的第一数据和第一纠错码。 第二非易失性存储器存储对于具有比第一纠错码更高的校正能力的第一数据产生的第二纠错码。 第一纠错单元通过使用第一纠错码对第一数据进行纠错。 第二纠错单元通过使用第二纠错码对第一数据进行纠错。 接口将纠错后的第一个数据发送给主机。
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