公开(公告)号：US12216942B2

公开(公告)日：2025-02-04

申请号：US18483468

申请日：2023-10-09

Applicant: Kioxia Corporation

Inventor： Yoshihiro Ohba ,  Tomoya Sanuki ,  Takeshi Ishihara

IPC: G06F3/06

Abstract: According to one embodiment, a controller includes a first interface, a second interface, a virtual register table, a memory management unit and a calculation processing unit. The first interface receives an I/O command from a host. The second interface transmits and receives first host data to and from a storage. The virtual register table has a virtual address specified by a page number assigned to a page in which data to be used to process a calculation instruction is stored and a page offset, and a data size of the data. The memory management unit stores, into a memory, the copy of the first host data, and updates the virtual register table. The calculation processing unit processes the calculation instruction by referring to the virtual register table.

公开(公告)号：US20240371849A1

公开(公告)日：2024-11-07

申请号：US18778420

申请日：2024-07-19

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

公开(公告)号：US11574663B2

公开(公告)日：2023-02-07

申请号：US17109853

申请日：2020-12-02

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Tomoya Sanuki ,  Takashi Maeda ,  Go Shikata ,  Hideaki Aochi

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US11411016B2

公开(公告)日：2022-08-09

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Hiroshi Maejima ,  Kenichiro Yoshii ,  Takashi Maeda ,  Hideo Wada

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11563 ,  H01L27/11568

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

公开(公告)号：US12219767B2

公开(公告)日：2025-02-04

申请号：US18523494

申请日：2023-11-29

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H10B43/27 ,  G11C5/06 ,  H01L23/00 ,  H01L25/065

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

公开(公告)号：US11942176B2

公开(公告)日：2024-03-26

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Xu Li ,  Masayuki Miura ,  Takayuki Miyazaki ,  Toshio Fujisawa ,  Hiroto Nakai ,  Hideko Mukaida ,  Mie Matsuo

IPC: G11C5/00 ,  G11C5/14 ,  G11C16/30 ,  H02M3/158 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C5/14 ,  G11C16/30 ,  H02M3/1582 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US11871576B2

公开(公告)日：2024-01-09

申请号：US17113285

申请日：2020-12-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Mie Matsuo ,  Kenichiro Yoshii ,  Koichiro Shindo ,  Kazushige Kawasaki ,  Tomoya Sanuki

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US11508697B2

公开(公告)日：2022-11-22

申请号：US16806079

申请日：2020-03-02

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Hiroshi Maejima ,  Tetsuaki Utsumi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

公开(公告)号：US12190966B2

公开(公告)日：2025-01-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Hitomi Tanaka ,  Tatsuro Hitomi ,  Yasuhito Yoshimizu ,  Masayuki Miura ,  Yoshihiro Ohba

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H10B43/00

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

公开(公告)号：US20240201660A1

公开(公告)日：2024-06-20

申请号：US18592235

申请日：2024-02-29

Applicant: Kioxia Corporation

Inventor： Tatsuro Hitomi ,  Yasuhito Yoshimizu ,  Masayuki Miura ,  Mitoshi Miyaoka ,  Tetsuharu Kojima ,  Tomoya Sanuki

IPC: G05B19/4155

CPC classification number: G05B19/4155 ,  G05B2219/40036

Abstract: According to one embodiment, a package stocker is configured to store a plurality of semiconductor packages each including one or more nonvolatile memory dies. A drive includes at least one socket on which a semiconductor package is able to be detachably mounted. A host apparatus, which is communicatively connected to the drive, reads/writes data from/to the one or more nonvolatile memory dies of the semiconductor package mounted on the socket. When a first semiconductor package is not mounted on the socket, the host apparatus causes a package transport device to transport the first semiconductor package to the drive and to mount the first semiconductor package on the socket.