公开(公告)号：US12190966B2

公开(公告)日：2025-01-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Hitomi Tanaka ,  Tatsuro Hitomi ,  Yasuhito Yoshimizu ,  Masayuki Miura ,  Yoshihiro Ohba

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H10B43/00

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

公开(公告)号：US20240201660A1

公开(公告)日：2024-06-20

申请号：US18592235

申请日：2024-02-29

Applicant: Kioxia Corporation

Inventor： Tatsuro Hitomi ,  Yasuhito Yoshimizu ,  Masayuki Miura ,  Mitoshi Miyaoka ,  Tetsuharu Kojima ,  Tomoya Sanuki

IPC: G05B19/4155

CPC classification number: G05B19/4155 ,  G05B2219/40036

Abstract: According to one embodiment, a package stocker is configured to store a plurality of semiconductor packages each including one or more nonvolatile memory dies. A drive includes at least one socket on which a semiconductor package is able to be detachably mounted. A host apparatus, which is communicatively connected to the drive, reads/writes data from/to the one or more nonvolatile memory dies of the semiconductor package mounted on the socket. When a first semiconductor package is not mounted on the socket, the host apparatus causes a package transport device to transport the first semiconductor package to the drive and to mount the first semiconductor package on the socket.

公开(公告)号：US11929332B2

公开(公告)日：2024-03-12

申请号：US17189718

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Soichi Homma ,  Tatsuo Migita ,  Masayuki Miura ,  Takeori Maeda ,  Kazuhiro Kato ,  Susumu Yamamoto

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13026 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

公开(公告)号：US11923325B2

公开(公告)日：2024-03-05

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: H01L23/00 ,  G06F11/07 ,  H01L23/544

CPC classification number: H01L24/05 ,  G06F11/073 ,  G06F11/0751 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2924/14511

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US11239223B2

公开(公告)日：2022-02-01

申请号：US16782710

申请日：2020-02-05

Applicant: KIOXIA CORPORATION

Inventor： Masayuki Miura

IPC: H01L25/18 ,  H01L23/24 ,  H01L23/00 ,  H01L25/00

Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.

公开(公告)号：US11894358B2

公开(公告)日：2024-02-06

申请号：US17562549

申请日：2021-12-27

Applicant: KIOXIA CORPORATION

Inventor： Masayuki Miura

IPC: H01L25/18 ,  H01L23/24 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/24 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/73265

Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.

公开(公告)号：US11422712B2

公开(公告)日：2022-08-23

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

公开(公告)号：US11942176B2

公开(公告)日：2024-03-26

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Xu Li ,  Masayuki Miura ,  Takayuki Miyazaki ,  Toshio Fujisawa ,  Hiroto Nakai ,  Hideko Mukaida ,  Mie Matsuo

IPC: G11C5/00 ,  G11C5/14 ,  G11C16/30 ,  H02M3/158 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C5/14 ,  G11C16/30 ,  H02M3/1582 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US11705434B2

公开(公告)日：2023-07-18

申请号：US17459376

申请日：2021-08-27

Applicant: Kioxia Corporation

Inventor： Masayuki Miura ,  Yuichi Sano ,  Kazuma Hasegawa

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562

Abstract: A semiconductor device includes a first stacked body including first semiconductor chips stacked in a first direction and offset relative to each other in a second direction; a first columnar electrode coupled to the first semiconductor chip and extending in the first direction; a second stacked body arranged relative to the first stacked body in the second direction and including second semiconductor chips stacked in the first direction and offset relative to each other in the second direction; a second columnar electrode coupled to the second semiconductor chip and extending in the first direction; and a third semiconductor chip arranged substantially equally spaced to the first columnar electrode and the second columnar electrode.

公开(公告)号：US11568901B2

公开(公告)日：2023-01-31

申请号：US17470955

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kazushige Kawasaki ,  Masayuki Miura ,  Hideko Mukaida

IPC: G11C5/06 ,  H01L23/10

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0≤t1