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公开(公告)号：US12223997B2
公开(公告)日：2025-02-11
申请号：US18490148
申请日：2023-10-19
Applicant: Kioxia Corporation
Inventor： Toshifumi Watanabe , Naofumi Abiko
IPC: G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4094 , G11C11/56 , G06F3/06 , G06F11/10 , G11C5/14 , G11C7/12 , G11C8/08 , G11C16/04
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US11842759B2
公开(公告)日：2023-12-12
申请号：US17873427
申请日：2022-07-26
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi Watanabe , Naofumi Abiko
IPC: G11C16/04 , G11C16/26 , G11C11/4094 , G11C16/24 , G11C5/14 , G11C7/12 , G11C7/00 , G11C7/06 , G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C8/08 , G06F3/06 , G06F11/10
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4094 , G11C11/5628 , G11C11/5642 , G06F3/0688 , G06F11/1072 , G11C5/147 , G11C7/12 , G11C8/08 , G11C16/0483
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US12198767B2
公开(公告)日：2025-01-14
申请号：US18243258
申请日：2023-09-07
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
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公开(公告)号：US12028068B2
公开(公告)日：2024-07-02
申请号：US18178038
申请日：2023-03-03
Applicant: Kioxia Corporation
Inventor： Fumiya Watanabe , Toshifumi Watanabe , Kazuhiko Satou , Shouichi Ozaki , Kenro Kubota , Atsuko Saeki , Ryota Tsuchiya , Harumi Abe
CPC classification number: H03K3/011 , G11C7/1048 , H03K17/14 , G11C2207/2254 , H03K19/20
Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.
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Patent Agency Ranking
公开(公告)号：US11430502B2
公开(公告)日：2022-08-30
申请号：US17222969
申请日：2021-04-05
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi Watanabe , Naofumi Abiko
IPC: G11C16/04 , G11C16/26 , G11C11/4094 , G11C16/24 , G11C5/14 , G11C7/12 , G11C7/00 , G11C7/06 , G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C8/08 , G06F3/06 , G06F11/10
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US11810629B2
公开(公告)日：2023-11-07
申请号：US17899971
申请日：2022-08-31
Applicant: KIOXIA CORPORATION
Inventor： Takeshi Hioka , Toshifumi Watanabe
CPC classification number: G11C16/3459 , G11C7/06 , G11C16/102 , G11C16/3404
Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.
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公开(公告)号：US11532363B2
公开(公告)日：2022-12-20
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US11024360B2
公开(公告)日：2021-06-01
申请号：US16799402
申请日：2020-02-24
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi Watanabe , Naofumi Abiko
IPC: G11C16/04 , G11C16/26 , G11C11/4094 , G11C16/24 , G11C5/14 , G11C7/12 , G11C7/00 , G11C7/06 , G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C8/08 , G06F3/06 , G06F11/10
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US11783899B2
公开(公告)日：2023-10-10
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
CPC classification number: G11C16/14 , G11C16/26 , G11C16/30 , G11C16/3445
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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