SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

    公开(公告)号:US20240404920A1

    公开(公告)日:2024-12-05

    申请号:US18807170

    申请日:2024-08-16

    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

    MEMORY DEVICE CONFIGURED TO PERFORM A SEARCH OPERATION

    公开(公告)号:US20240304239A1

    公开(公告)日:2024-09-12

    申请号:US18587935

    申请日:2024-02-26

    CPC classification number: G11C11/4096 G11C11/4074 G11C11/4085

    Abstract: A memory device includes a bit line, a source line, a first string in which a plurality of first memory cells are connected in series between the bit line and the source line, and a control circuit. The control circuit performs a sense operation for a search operation to determine if search data is stored in the plurality of first memory cells by supplying voltages to a plurality of word lines respectively corresponding to the plurality of first memory cells based on the search data and determining a similarity between the search data and data actually stored in the plurality of first memory cells based on a change in voltage of the bit line caused by current flowing between the bit line and the source line via the first string.

    SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请

    公开(公告)号:US20210296349A1

    公开(公告)日:2021-09-23

    申请号:US17172947

    申请日:2021-02-10

    Abstract: A semiconductor storage device includes a substrate with a memory cell region and a first region to one side of the memory cell region. A first memory cell layer is on the substrate. A second memory cell layer is between the first memory cell layer and the substrate. A plurality of first conductive layers are stacked on each other in the first memory cell layer. A plurality of second conductive layers are stacked on each other in the second memory cell layer. A plurality of first contacts are above the first region of the substrate, extending through second conductive layer from the substrate to the first memory cell layer. The contacts are electrically insulated from the second conductive layers and electrically connected to ends of the first conductive layers in the first region.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20210074643A1

    公开(公告)日:2021-03-11

    申请号:US17004345

    申请日:2020-08-27

    Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

    公开(公告)号:US20230114433A1

    公开(公告)日:2023-04-13

    申请号:US18079054

    申请日:2022-12-12

    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body.
    A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

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