公开(公告)号：US20240071478A1

公开(公告)日：2024-02-29

申请号：US18504018

申请日：2023-11-07

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA ,  Yoshinao SUZUKI ,  Mai SHIMIZU ,  Kazuyoshi MURAOKA ,  Masami MASUDA ,  Yoshikazu HOSOMURA

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4076

Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

公开(公告)号：US20230083392A1

公开(公告)日：2023-03-16

申请号：US17680144

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HOSOMURA ,  Hideyuki KATAOKA ,  Yoshinao SUZUKI ,  Mai SHIMIZU ,  Kazuyoshi MURAOKA ,  Masami MASUDA

IPC: H01L27/11524 ,  G11C16/04 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

公开(公告)号：US20220223611A1

公开(公告)日：2022-07-14

申请号：US17369453

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Takatoshi MINAMOTO ,  Sho TOKAIRIN ,  Yoshinao SUZUKI

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source.

公开(公告)号：US20220238167A1

公开(公告)日：2022-07-28

申请号：US17461848

申请日：2021-08-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshinao SUZUKI ,  Haruka SHIBAYAMA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.

公开(公告)号：US20220076734A1

公开(公告)日：2022-03-10

申请号：US17184123

申请日：2021-02-24

Applicant: Kioxia Corporation

Inventor： Yoshinao SUZUKI

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/06

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US20240233835A1

公开(公告)日：2024-07-11

申请号：US18408680

申请日：2024-01-10

Applicant: Kioxia Corporation

Inventor： Yoshinao SUZUKI ,  Kazuto SHITARA ,  Kenta SHIBASAKI ,  Noriyasu KUMAZAKI

IPC: G11C16/30 ,  G11C16/04 ,  H02M3/07

CPC classification number: G11C16/30 ,  G11C16/0483 ,  H02M3/07 ,  G11C16/26

Abstract: A semiconductor device includes a regulator circuit, a charge pump circuit, and a control circuit. The regulator circuit is configured to regulate a voltage input from outside and output a regulated voltage. The charge pump circuit is configured to receive the regulated voltage as an input voltage, boost the input voltage, and output a boosted voltage. The control circuit is configured to cause the regulator circuit to vary a voltage level of the regulated voltage based on voltage value information about the voltage input from the outside.

公开(公告)号：US20230062829A1

公开(公告)日：2023-03-02

申请号：US17665391

申请日：2022-02-04

Applicant: KIOXIA CORPORATION

Inventor： Yoshinao SUZUKI

IPC: G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.