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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    1.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION 有权

    公开(公告)号：US20240420774A1

    公开(公告)日：2024-12-19

    申请号：US18815433

    申请日：2024-08-26

    Applicant: KIOXIA CORPORATION

    Inventor： Jun NAKAI ,  Noboru SHIBATA

    IPC: G11C16/16 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

    MEMORY DEVICE
    2.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240265984A1

    公开(公告)日：2024-08-08

    申请号：US18432269

    申请日：2024-02-05

    Applicant: Kioxia Corporation

    Inventor： Noboru SHIBATA ,  Kikuko SUGIMAE ,  Yusuke ARAYASHIKI ,  Katsuya NISHIYAMA ,  Motohiko FUJIMATSU ,  Akiyuki MURAYAMA

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26

    Abstract: According to one embodiment, a memory device includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or larger). The sequencer is configured to execute a write operation having a loop process including a program operation and a verify operation. The program operation includes a first program process and a second program process. The sequencer is further configured to cause the first memory cell to store data by either the first program process or the second program process according to data to be written into the first memory cell in the write operation.

    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME 审中-公开

    公开(公告)号：US20240047001A1

    公开(公告)日：2024-02-08

    申请号：US18486433

    申请日：2023-10-13

    Applicant: Kioxia Corporation

    Inventor： Noboru SHIBATA

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3445 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230245697A1

    公开(公告)日：2023-08-03

    申请号：US18131511

    申请日：2023-04-06

    Applicant: Kioxia Corporation

    Inventor： Noboru SHIBATA

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C11/5635 ,  G11C11/5642 ,  G11C16/3459 ,  G11C16/10 ,  G11C11/5628 ,  G11C16/0483

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

    SEMICONDUCTOR MEMORY
    6.
    发明申请
    SEMICONDUCTOR MEMORY 有权

    公开(公告)号：US20210264990A1

    公开(公告)日：2021-08-26

    申请号：US17244246

    申请日：2021-04-29

    Applicant: Kioxia Corporation

    Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

    IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  H01L27/115

    Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

    MEMORY SYSTEM
    7.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230410899A1

    公开(公告)日：2023-12-21

    申请号：US18364524

    申请日：2023-08-03

    Applicant: KIOXIA CORPORATION

    Inventor： Tokumasa HARA ,  Noboru SHIBATA

    IPC: G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/0679

    Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND WRITE METHOD
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND WRITE METHOD 有权

    公开(公告)号：US20220366973A1

    公开(公告)日：2022-11-17

    申请号：US17874968

    申请日：2022-07-27

    Applicant: Kioxia Corporation

    Inventor： Noboru SHIBATA ,  Yasuyuki MATSUDA

    IPC: G11C11/56 ,  G11C11/408 ,  G11C16/08

    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

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