公开(公告)号：US20130048605A1

公开(公告)日：2013-02-28

申请号：US13593412

申请日：2012-08-23

申请人： Kedar SAPRE ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

发明人： Kedar SAPRE ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

IPC分类号： B44C1/22

CPC分类号： H01L21/31144 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116

摘要： A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.

摘要翻译： 蚀刻衬底的方法包括在衬底上形成由氧化硅，氮化硅或氮氧化硅组成的多个双重构图特征。 具有双重图案化特征的基板被提供到处理区域。 包括三氟化氮，氨和氢的蚀刻气体在远程室中通电。 通电的蚀刻气体被引入到工艺区中以蚀刻双重图案化特征以在衬底上形成固体残余物。 固体残余物通过将基底加热至至少约100℃的温度升华。

公开(公告)号：US08759223B2

公开(公告)日：2014-06-24

申请号：US13593412

申请日：2012-08-23

申请人： Kedar Sapre ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

发明人： Kedar Sapre ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116

摘要： A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.

摘要翻译： 蚀刻衬底的方法包括在衬底上形成由氧化硅，氮化硅或氮氧化硅组成的多个双重构图特征。 具有双重图案化特征的基板被提供到处理区域。 包括三氟化氮，氨和氢的蚀刻气体在远程室中通电。 通电的蚀刻气体被引入到工艺区中以蚀刻双重图案化特征以在衬底上形成固体残余物。 固体残余物通过将基底加热至至少约100℃的温度升华。

公开(公告)号：US08435902B2

公开(公告)日：2013-05-07

申请号：US12959155

申请日：2010-12-02

申请人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

发明人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  C23F3/00

CPC分类号： H01L21/31116 ,  H01J37/32091

摘要： A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

摘要翻译： 描述了从窄沟槽和宽沟槽（或开放区域）中蚀刻氧化硅的方法，其允许宽沟槽中的蚀刻比窄沟槽中的蚀刻进一步进行。 该方法包括两个干蚀刻循环。 第一干蚀刻循环涉及低强度或缩写升华步骤，其在窄沟槽中留下固体残留物。 剩余的固体残余物在第二干蚀刻循环期间抑制窄沟槽中的蚀刻进程，允许宽沟槽中的蚀刻超过窄沟槽中的蚀刻。

公开(公告)号：US20110230052A1

公开(公告)日：2011-09-22

申请号：US12959155

申请日：2010-12-02

申请人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

发明人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

IPC分类号： H01L21/3065

CPC分类号： H01L21/31116 ,  H01J37/32091

摘要： A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

摘要翻译： 描述了从窄沟槽和宽沟槽（或开放区域）中蚀刻氧化硅的方法，其允许宽沟槽中的蚀刻比窄沟槽中的蚀刻进一步进行。 该方法包括两个干蚀刻循环。 第一干蚀刻循环涉及低强度或缩写升华步骤，其在窄沟槽中留下固体残留物。 剩余的固体残余物在第二干蚀刻循环期间抑制窄沟槽中的蚀刻进程，允许宽沟槽中的蚀刻超过窄沟槽中的蚀刻。

公开(公告)号：US08236708B2

公开(公告)日：2012-08-07

申请号：US12855877

申请日：2010-08-13

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/316 ,  C23C16/40

CPC分类号： H01L21/02219 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271

摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积电介质层的方法。 在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。 根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

公开(公告)号：US07994019B1

公开(公告)日：2011-08-09

申请号：US12891149

申请日：2010-09-27

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/00

CPC分类号： H01L21/02164 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/0228

摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。 在实施例中，通过将含硅前体和臭氧流入处理室来沉积电介质层，使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。 根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性，同时仍然适用于非牺牲应用。 依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。 多个沉积循环可以串联进行，因为在沉积停顿之后潜伏期的有益特性可以重复。

公开(公告)号：US20110223774A1

公开(公告)日：2011-09-15

申请号：US12855877

申请日：2010-08-13

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/316

CPC分类号： H01L21/02219 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271

摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积电介质层的方法。 在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。 根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

公开(公告)号：US20050255667A1

公开(公告)日：2005-11-17

申请号：US10846734

申请日：2004-05-14

申请人： Reza Arghavani ,  Zheng Yuan ,  Ellie Yieh ,  Shankar Venkataraman ,  Nitin Ingle

发明人： Reza Arghavani ,  Zheng Yuan ,  Ellie Yieh ,  Shankar Venkataraman ,  Nitin Ingle

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/00 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

摘要： A method of fabricating a semiconductor device, where the method includes forming on a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.

摘要翻译： 一种制造半导体器件的方法，其中所述方法包括在衬底上的晶体管上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间导电的沟道区域，形成与所述晶体管相邻的沟槽， 材料在衬底上并在沟槽内，并退火材料，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。 另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料 在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

公开(公告)号：US20120009796A1

公开(公告)日：2012-01-12

申请号：US12909167

申请日：2010-10-21

申请人： Zhenjiang Cui ,  Anchuan Wang ,  Mehul Naik ,  Nitin Ingle ,  Young Lee ,  Shankar Venkataraman

发明人： Zhenjiang Cui ,  Anchuan Wang ,  Mehul Naik ,  Nitin Ingle ,  Young Lee ,  Shankar Venkataraman

IPC分类号： H01L21/3065

CPC分类号： H01L21/3105 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76814

摘要： Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.

摘要翻译： 描述了降低集成电路的两个导电部件之间存在的有效介电常数的方法。 该方法包括使用对低K电介质层的富氧部分具有选择性的气相蚀刻。 当蚀刻工艺通过较高K富氧部分并达到低K部分时，蚀刻速率衰减。 由于气相蚀刻工艺不容易除去所需的低K部分，所以蚀刻工艺可以容易地定时。

公开(公告)号：US06379492B2

公开(公告)日：2002-04-30

申请号：US09428140

申请日：1999-10-26

申请人： Won Bang ,  Chen-An Chen ,  Shankar Venkataraman ,  Ajay Bhatnagar

发明人： Won Bang ,  Chen-An Chen ,  Shankar Venkataraman ,  Ajay Bhatnagar

IPC分类号： C23F102

CPC分类号： C23C14/5806 ,  C23C14/0694 ,  C23C16/4404 ,  H01J37/32477 ,  H01J37/32559

摘要： A corrosion resistant part comprising a protective coating formed upon a component part. The protective coating comprises magnesium fluoride, which is substantially pure and substantially dense. Preferably, the coating is at least about 99% pure and at least about 85% dense. For example, such a coating can be formed upon the component part at a temperature of at least about 250° C. and a pressure of not more than about 1×10−5 torr. The resulting coating is effective in protecting the surfaces of an aluminum nitride heater against corrosion within a fluorine-containing environment inside a chemical vapor deposition chamber.

摘要翻译： 一种耐腐蚀部件，包括形成在部件上的保护涂层。 保护性涂层包括氟化镁，其基本上纯且基本上致密。 优选地，涂层为至少约99％纯度且至少约85％致密。 例如，这样的涂层可以在至少约250℃的温度和不大于约1×10-5乇的压力下在组分部分上形成。 所得到的涂层有效地保护氮化铝加热器的表面免受化学气相沉积室内的含氟环境中的腐蚀。