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公开(公告)号:US20240404920A1
公开(公告)日:2024-12-05
申请号:US18807170
申请日:2024-08-16
Applicant: Kioxia Corporation
Inventor: Yasuhito YOSHIMIZU , Yoshiro SHIMOJO , Shinya ARAI
IPC: H01L23/48 , H01L21/768 , H01L23/522 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
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公开(公告)号:US20240304239A1
公开(公告)日:2024-09-12
申请号:US18587935
申请日:2024-02-26
Applicant: Kioxia Corporation
Inventor: Tomoya SANUKI , Yasuhito YOSHIMIZU
IPC: G11C11/4096 , G11C11/4074 , G11C11/408
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4085
Abstract: A memory device includes a bit line, a source line, a first string in which a plurality of first memory cells are connected in series between the bit line and the source line, and a control circuit. The control circuit performs a sense operation for a search operation to determine if search data is stored in the plurality of first memory cells by supplying voltages to a plurality of word lines respectively corresponding to the plurality of first memory cells based on the search data and determining a similarity between the search data and data actually stored in the plurality of first memory cells based on a change in voltage of the bit line caused by current flowing between the bit line and the source line via the first string.
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公开(公告)号:US20230324455A1
公开(公告)日:2023-10-12
申请号:US18209398
申请日:2023-06-13
Applicant: Kioxia Corporation
Inventor: Tatsuro HITOMI , Yasuhito YOSHIMIZU , Masayuki MIURA , Arata INOUE , Hiroyuki DOHMAE , Koichi NAKAZAWA , Mitoshi MIYAOKA , Kazuhito HAYASAKA , Tomoya SANUKI
CPC classification number: G01R31/2886 , G01R1/07342
Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.
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公开(公告)号:US20230282289A1
公开(公告)日:2023-09-07
申请号:US17899447
申请日:2022-08-30
Applicant: KIOXIA CORPORATION
Inventor: Tomoya SANUKI , Hitomi TANAKA , Tatsuro HITOMI , Yasuhito YOSHIMIZU , Masayuki MIURA , Yoshihiro OHBA
IPC: G11C16/26 , G11C16/34 , G06F3/06 , H01L27/11563
CPC classification number: G11C16/26 , G06F3/0679 , G11C16/34 , H01L27/11563
Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.
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公开(公告)号:US20210296349A1
公开(公告)日:2021-09-23
申请号:US17172947
申请日:2021-02-10
Applicant: KIOXIA CORPORATION
Inventor: Yasuhito YOSHIMIZU
IPC: H01L27/11578 , H01L27/11573 , H01L27/11551 , H01L27/11526 , H01L27/11519 , H01L27/11565
Abstract: A semiconductor storage device includes a substrate with a memory cell region and a first region to one side of the memory cell region. A first memory cell layer is on the substrate. A second memory cell layer is between the first memory cell layer and the substrate. A plurality of first conductive layers are stacked on each other in the first memory cell layer. A plurality of second conductive layers are stacked on each other in the second memory cell layer. A plurality of first contacts are above the first region of the substrate, extending through second conductive layer from the substrate to the first memory cell layer. The contacts are electrically insulated from the second conductive layers and electrically connected to ends of the first conductive layers in the first region.
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公开(公告)号:US20210074643A1
公开(公告)日:2021-03-11
申请号:US17004345
申请日:2020-08-27
Applicant: Kioxia Corporation
Inventor: Takashi WATANABE , Yasuhito YOSHIMIZU
IPC: H01L23/538 , H01L27/11556 , H01L27/11582 , G11C5/02 , H01L21/768
Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.
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公开(公告)号:US20240355743A1
公开(公告)日:2024-10-24
申请号:US18760442
申请日:2024-07-01
Applicant: Kioxia Corporation
Inventor: Yasuhito YOSHIMIZU
IPC: H01L23/535 , H01L21/768 , H01L23/00 , H01L23/522 , H01L25/065 , H01L25/18 , H10B43/27
CPC classification number: H01L23/535 , H01L21/76805 , H01L21/76895 , H01L23/5226 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B43/27 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor storage device includes a semiconductor substrate and a conductive layer separated from the semiconductor substrate in a first direction. The conductive layer extends in a second direction parallel to the semiconductor substrate. A semiconductor layer extends in the first direction through the conductive layer. A first contact extends in the first direction and is connected to a surface of the conductive layer facing away from the semiconductor substrate. A first insulating layer extends in the first direction, and a second insulating layer extends along the first insulating layer in the first direction. Each of the first and second insulating layers entirely overlaps with the first contact when viewed in the first direction.
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公开(公告)号:US20240188253A1
公开(公告)日:2024-06-06
申请号:US18461563
申请日:2023-09-06
Applicant: Kioxia Corporation
Inventor: Tomoya SANUKI , Yasuhito YOSHIMIZU , Yusuke HIGASHI , Hideko MUKAIDA
IPC: H05K7/20
CPC classification number: H05K7/20372 , H05K7/20381
Abstract: A semiconductor device according to an embodiment includes: a chamber including an internal structure capable of holding a pressure in the chamber lower than atmospheric pressure; one or a plurality of cooling member provided inside of the internal structure of the chamber, the cooling member holding and cooling a semiconductor device; and a heat transfer part exchanging heat with a refrigerator cooling the cooling member.
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公开(公告)号:US20230114433A1
公开(公告)日:2023-04-13
申请号:US18079054
申请日:2022-12-12
Applicant: Kioxia Corporation
Inventor: Yasuhito YOSHIMIZU , Yoshiro Shimojo , Shinya Arai
IPC: H01L23/48 , H01L21/768 , H01L23/522
Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body.
A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.-
公开(公告)号:US20220223552A1
公开(公告)日:2022-07-14
申请号:US17695654
申请日:2022-03-15
Applicant: Kioxia Corporation
Inventor: Yasuhito YOSHIMIZU , Takashi FUKUSHIMA , Tatsuro HITOMI , Arata INOUE , Masayuki MIURA , Shinichi KANNO , Toshio FUJISAWA , Keisuke NAKATSUKA , Tomoya SANUKI
IPC: H01L23/00 , H01L23/544 , G06F11/07
Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
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