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    Method of trench filling
    2.
    发明授权
    Method of trench filling 失效
    沟槽填充方法

    公开(公告)号：US4924284A

    公开(公告)日：1990-05-08

    申请号：US145863

    申请日：1988-01-20

    申请人： Klaus D. Beyer ,  Victor J. Silvestri

    发明人： Klaus D. Beyer ,  Victor J. Silvestri

    IPC分类号： H01L21/76 ,  H01L21/225 ,  H01L21/74 ,  H01L21/763 ,  H01L29/41

    CPC分类号： H01L21/763 ,  H01L21/2255 ,  H01L21/743

    摘要： A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

    摘要翻译： 在要生产衬底接触的区域和在其他区域中的沟槽隔离的同时产生掺杂的硅填充沟槽的方法。 硼硅酸盐玻璃将需要接触的那些沟槽的侧壁进行配线，并且未掺杂的外延生长的硅填充所有沟槽。 随后的热处理使硼硅酸盐中的硼掺杂在那些沟槽中的外延硅。 在其他沟槽中，除了存在通道停止的底部之外，硅填充物保持未掺杂，从而形成隔离沟槽。 可以通过选择性地将高度掺杂的硅沉积到覆盖在沟槽和相邻衬底表面的一部分的开口中而形成在沟槽上形成的触点。

    Method of producing a thin silicon-on-insulator layer
    3.
    发明授权
    Method of producing a thin silicon-on-insulator layer 失效
    制造薄的绝缘体上硅层的方法

    公开(公告)号：US5234535A

    公开(公告)日：1993-08-10

    申请号：US988655

    申请日：1992-12-10

    申请人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

    发明人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/762

    CPC分类号： H01L21/2007 ,  H01L21/76251 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/981

    摘要： A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of:a) providing a first wafer comprising a silicon substrate of a first conductivity type, a diffusion layer of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer formed upon the thin epitaxial layer;b) providing a second wafer comprising a silicon substrate having a thin oxide layer formed on a surface thereof;c) wafer bonding said first wafer to said second wafer;d) removing the silicon substrate of said first wafer in a controlled mechanical manner; ande) removing the diffusion layer of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer, the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer.

    Method for forming a void free isolation structure utilizing etch and refill techniques
    4.
    发明授权
    Method for forming a void free isolation structure utilizing etch and refill techniques 失效
    使用蚀刻和再填充技术形成无空隙隔离结构的方法

    公开(公告)号：US4528047A

    公开(公告)日：1985-07-09

    申请号：US624425

    申请日：1984-06-25

    申请人： Klaus D. Beyer ,  Victor J. Silvestri

    发明人： Klaus D. Beyer ,  Victor J. Silvestri

    IPC分类号： H01L21/76 ,  H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/302

    CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/025 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/085

    摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

    摘要翻译： 描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。 隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。 第一绝缘层位于沟槽的侧壁上。 沟槽的底部或底部对单晶半导体体是开放的。 从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。 沟槽宽度x的优选范围为约10微米或更小。 多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。 第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。 密封的外延单晶半导体防止在沟槽图案内形成空隙。 外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

    Method of trench filling
    7.
    发明授权
    Method of trench filling 失效

    公开(公告)号：US4745081A

    公开(公告)日：1988-05-17

    申请号：US793518

    申请日：1985-10-31

    申请人： Klaus D. Beyer ,  Victor J. Silvestri

    发明人： Klaus D. Beyer ,  Victor J. Silvestri

    IPC分类号： H01L21/76 ,  H01L21/225 ,  H01L21/74 ,  H01L21/763 ,  H01L29/41 ,  H01L21/36 ,  H01L21/425

    CPC分类号： H01L21/763 ,  H01L21/2255 ,  H01L21/743

    摘要： A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

    Planar void free isolation structure
    8.
    发明授权
    Planar void free isolation structure 失效
    平面无空隙隔离结构

    公开(公告)号：US4680614A

    公开(公告)日：1987-07-14

    申请号：US711554

    申请日：1985-03-14

    申请人： Klaus D. Beyer ,  Victor J. Silvestri

    发明人： Klaus D. Beyer ,  Victor J. Silvestri

    IPC分类号： H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/95 ,  H01L27/04

    CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S148/131

    摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

    摘要翻译： 描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。 隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。 第一绝缘层位于沟槽的侧壁上。 沟槽的底部或底部对单晶半导体体是开放的。 从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。 沟槽宽度x的优选范围为约10微米或更小。 多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。 第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。 密封的外延单晶半导体防止在沟槽图案内形成空隙。 外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

    Reach-through isolation silicon-on-insulator device
    9.
    发明授权
    Reach-through isolation silicon-on-insulator device 失效
    隔离绝缘体上的隔离器器件

    公开(公告)号：US5391911A

    公开(公告)日：1995-02-21

    申请号：US231100

    申请日：1994-04-22

    申请人： Klaus D. Beyer ,  Andrie S. Yapsir

    发明人： Klaus D. Beyer ,  Andrie S. Yapsir

    IPC分类号： H01L21/764 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L27/04

    CPC分类号： H01L21/76264 ,  H01L21/76289 ,  Y10S148/05 ,  Y10S148/164

    摘要： A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

    摘要翻译： 一种方法和所得到的产品，用于将共同的衬底彼此分离轻掺杂的硅岛。 衬底被第一重掺杂外延层覆盖。 第一层被轻掺杂的第二外延层覆盖。 提供一对间隔的深沟槽，其从第二层的顶表面延伸穿过第一层并进入衬底。 沟槽的内壁衬有氧化物。 从所述顶表面延伸到第一层的一对重掺杂的贯穿扩散层垂直于深沟槽定向并在沟槽之间完全延伸。 通过单个各向异性蚀刻步骤去除重掺杂的通孔扩散和相邻的第一层，以产生除空气与氧化物衬里的深沟槽接触的空气，由空气隔离。 空气隔离优选地部分地被其它介电材料替代。