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309 条记录 (耗时 0.058 秒)

    Bonded wafer structure having a buried insulation layer
    2.
    发明授权
    Bonded wafer structure having a buried insulation layer 失效
    具有掩埋绝缘层的粘合晶片结构

    公开(公告)号：US5276338A

    公开(公告)日：1994-01-04

    申请号：US883082

    申请日：1992-05-15

    申请人： Klaus Beyer ,  Chang-Ming Hsieh ,  Louis L. Hsu ,  Tsorng-Dih Yuan

    发明人： Klaus Beyer ,  Chang-Ming Hsieh ,  Louis L. Hsu ,  Tsorng-Dih Yuan

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

    CPC分类号： H01L21/76264 ,  H01L21/2007 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/135

    摘要： A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

    摘要翻译： 可以形成半导体器件的晶片结构及其制造方法包括第一和第二晶片。 第一晶片包括在其底表面上形成有薄氧化物层的第一衬底，第一衬底具有特征热膨胀系数。 第二晶片包括具有形成在其顶表面上的绝缘层的第二基板，所述绝缘层具有与第一基板的特征热膨胀系数基本匹配并且还具有高导热性的特征热膨胀系数。 第二晶片还包括在绝缘层的顶表面上形成的薄氧化物层，其中第一晶片的第一薄氧化物层结合到第二晶片的第二薄氧化物层。

    Method of forming a SOI transistor having a self-aligned body contact
    3.
    发明授权
    Method of forming a SOI transistor having a self-aligned body contact 失效
    形成具有自对准体接触的SOI晶体管的方法

    公开(公告)号：US5405795A

    公开(公告)日：1995-04-11

    申请号：US268380

    申请日：1994-06-29

    申请人： Klaus D. Beyer ,  Taqi N. Buti ,  Chang-Ming Hsieh ,  Louis L. Hsu

    发明人： Klaus D. Beyer ,  Taqi N. Buti ,  Chang-Ming Hsieh ,  Louis L. Hsu

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/265

    CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

    摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

    摘要翻译： SOI晶体管具有通过对门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案 通过来源联系。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。

    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    5.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效

    公开(公告)号：US07052937B2

    公开(公告)日：2006-05-30

    申请号：US10429758

    申请日：2003-05-05

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

    Air-filled isolation trench with chemically vapor deposited silicon dioxide cap
    9.
    发明授权
    Air-filled isolation trench with chemically vapor deposited silicon dioxide cap 失效
    充气隔离沟槽，化学气相沉积二氧化硅盖

    公开(公告)号：US5098856A

    公开(公告)日：1992-03-24

    申请号：US717267

    申请日：1991-06-18

    申请人： Klaus D. Beyer ,  Louis L. Hsu ,  Subodh K. Kulkarni

    发明人： Klaus D. Beyer ,  Louis L. Hsu ,  Subodh K. Kulkarni

    IPC分类号： H01L21/76 ,  H01L21/764

    CPC分类号： H01L21/764

    摘要： A process for forming air-filled isolation trenches in a semiconductor substrate by a conformal chemical vapor deposition (CVD) of a silicon dioxide layer over the passivated surface of the semiconductor substrate in which intersecting trenches have been formed and partially filled with a material that can subsequentially be removed from under the CVD silicon dioxide layer, such materials include water soluble glasses and polymeric materials, such as a polyimide. The CVD silicon dioxide is etched back to the passivated surface of the semiconductor substrate, forming openings in the layer at the trench intersections that extend to the trench fill material. The fill material is removed through these openings. A CVD silicon dioxide layer is deposited to fill the openings, leaving a silicon dioxide cap bridging the air-filled trench. Water soluble glasses that may be used to fill the trench include BSG glass (B.sub.2 O.sub.3 content greater than 55%) and germanosilicate glass (GeO.sub.2 content greater than 50%). A polymer fill, such as a polyimide, if used, may be removed by plasma etching in O.sub.2.

    Method of producing a thin silicon-on-insulator layer
    10.
    发明授权
    Method of producing a thin silicon-on-insulator layer 失效
    制造薄的绝缘体上硅层的方法

    公开(公告)号：US5234535A

    公开(公告)日：1993-08-10

    申请号：US988655

    申请日：1992-12-10

    申请人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

    发明人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/762

    CPC分类号： H01L21/2007 ,  H01L21/76251 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/981

    摘要： A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of:a) providing a first wafer comprising a silicon substrate of a first conductivity type, a diffusion layer of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer formed upon the thin epitaxial layer;b) providing a second wafer comprising a silicon substrate having a thin oxide layer formed on a surface thereof;c) wafer bonding said first wafer to said second wafer;d) removing the silicon substrate of said first wafer in a controlled mechanical manner; ande) removing the diffusion layer of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer, the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer.