公开(公告)号：US20150256364A1

公开(公告)日：2015-09-10

申请号：US14248624

申请日：2014-04-09

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Vladimir Sindalovsky

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/03808

Abstract: Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over equalization, and a variable gain amplifier (VGA) in the receiver front end data path generally does not apply gain to amplify the signal back again due to the reduced DC level. GD-based TX post cursor adaptation may reduce over equalization effect and hence save power and increase performance by not over equalizing the signal.

Abstract translation: 描述的实施例提供了在基于组延迟（GD）的适配中的决策反馈均衡器（DFE）滤波器抽头和发射器（TX））后光标滤波的适配之间的去耦合。 因此，可以显着地减少或消除发射机后光标效应的过度建立及其由DFE的过度均衡消除。 通过断开该耦合，发射机不会使信号过度均衡，DFE不会尝试“撤消”过均衡，并且接收机前端数据通道中的可变增益放大器（VGA）通常不适用增益放大 由于降低的直流电平，再次发出信号。 基于GD的TX后光标自适应可以减少均衡效应，从而通过不使信号过度均衡来节省功率并提高性能。

公开(公告)号：US20160072650A1

公开(公告)日：2016-03-10

申请号：US14479278

申请日：2014-09-06

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Sunil Srinivasa ,  Vladimir Sindalovsky ,  Amaresh V. Malipatil ,  Pervez M. Aziz

IPC: H04L25/06 ,  H04L7/00

CPC classification number: H04L25/06 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0278 ,  H04L25/0292

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts termination impedance automatically to obtain a tuned termination. The termination adaptation is realized with a ‘biased’ bang-bang phase detector (BBPD) that biases the weights applied to UP and DOWN outputs of the phase detector. Through an optimization process, the system locks to data eye corners, and thereby is able to optimize termination though a predetermined criteria, such as signal to noise ratio (SNR), horizontal eye (H-) margin, vertical eye (V-) margin or joint SNR and H-/V-margin optimization. As part of the receiver equalization, adaptive termination tuning is performed after the SerDes receiver (RX) path is initially powered-up by tuning the termination above and below its current initial setting and performing the optimization process.

Abstract translation: 描述的实施例在SerDes设备中提供自适应调整终止阻抗以获得调谐终端的适配过程。 终端适配通过偏置的砰 - 相位相位检测器（BBPD）来实现，该相位检测器偏置施加到相位检测器的UP和DOWN输出的权重。 通过优化过程，系统锁定到数据眼角，从而能够通过诸如信噪比（SNR），水平眼（H）边缘，垂直眼（V-）边缘等预定标准来优化终止 或联合SNR和H / V边缘优化。 作为接收机均衡的一部分，在SerDes接收机（RX）路径最初上电之后，通过调谐高于和低于其当前初始设置的终止并执行优化过程来执行自适应终止调谐。

公开(公告)号：US20140233619A1

公开(公告)日：2014-08-21

申请号：US13768220

申请日：2013-02-15

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US20140097878A1

公开(公告)日：2014-04-10

申请号：US13647470

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Joseph Anidjar ,  Lane A. Smith ,  Brett David Hardy

IPC: H03L7/08

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/1075 ,  H03L7/146 ,  H03L2207/06

Abstract: In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain, change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Abstract translation: 在所描述的实施例中，用于SerDes设备的基于VCO的CDR包括相位检测器，响应于第一控制信号的VCO和第二控制信号并产生输出信号，频率校准模块被配置为通过以下步骤校准输出信号的频率 执行粗略校准和随后的精细校准，齿轮控制模块控制增益，第一和第二控制信号在时间上的变化，以及由从频率校准模块产生的精细校准值产生的查找表，其中， 通过采用存储在查找表中的精细校准值的计算电路来计算变速控制模块的编程可变增益，计算电路的计算调整换档降档，并且调整换档增益，并且调整总体 VCO控制曲线上的CDR增益。

公开(公告)号：US20150319018A1

公开(公告)日：2015-11-05

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。

公开(公告)号：US08953665B2

公开(公告)日：2015-02-10

申请号：US13768220

申请日：2013-02-15

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01 ,  H04L1/20

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US20140132320A1

公开(公告)日：2014-05-15

申请号：US13675520

申请日：2012-11-13

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。

公开(公告)号：US08816776B2

公开(公告)日：2014-08-26

申请号：US13675520

申请日：2012-11-13

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/085 ,  H04L7/033 ,  H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。

公开(公告)号：US09197460B1

公开(公告)日：2015-11-24

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。

公开(公告)号：US09172526B1

公开(公告)日：2015-10-27

申请号：US14340517

申请日：2014-07-24

Applicant: LSI Corporation

Inventor： Amaresh Malipatil ,  Sunil Srinivasa ,  Vladimir Sindalovsky ,  Mark Trafford

IPC: H04L7/04 ,  H04L7/033 ,  G06F1/10

CPC classification number: H04L7/04 ,  G06F1/10 ,  H04L7/033 ,  H04L25/03 ,  H04L25/03057

Abstract: Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a ‘biased’ bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

Abstract translation: 描述的实施例在接收机电路中提供自适应调整自适应IQ偏移以在数据眼中获得适当的眼睛定心，从而最大化眼睛的水平边缘。 IQ偏移自适应算法通过时钟和数据恢复电路（CDR）的“偏置”轰击相位检测器（BBPD）来实现，该电路偏置了施加到相位检测器的UP和DOWN输出的权重，而不是对它们进行处理 一样。 通过对BBPD UP和DOWN的加权不同，系统锁定到左右内角，从而能够定位内眼的中心。