公开(公告)号：US20140233619A1

公开(公告)日：2014-08-21

申请号：US13768220

申请日：2013-02-15

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US20140097878A1

公开(公告)日：2014-04-10

申请号：US13647470

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Joseph Anidjar ,  Lane A. Smith ,  Brett David Hardy

IPC: H03L7/08

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/1075 ,  H03L7/146 ,  H03L2207/06

Abstract: In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain, change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Abstract translation: 在所描述的实施例中，用于SerDes设备的基于VCO的CDR包括相位检测器，响应于第一控制信号的VCO和第二控制信号并产生输出信号，频率校准模块被配置为通过以下步骤校准输出信号的频率 执行粗略校准和随后的精细校准，齿轮控制模块控制增益，第一和第二控制信号在时间上的变化，以及由从频率校准模块产生的精细校准值产生的查找表，其中， 通过采用存储在查找表中的精细校准值的计算电路来计算变速控制模块的编程可变增益，计算电路的计算调整换档降档，并且调整换档增益，并且调整总体 VCO控制曲线上的CDR增益。

公开(公告)号：US08867602B1

公开(公告)日：2014-10-21

申请号：US14011236

申请日：2013-08-27

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Ye Liu ,  Brett D. Hardy ,  Lane A. Smith

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057

Abstract: A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.

Abstract translation: 公开了抽头系数控制电路和用于控制用于判决反馈均衡器的抽头系数的方法。 该方法包括基于第一抽头量化来调整施加到抽头系数的校正电压，并且检测判决反馈均衡器抽头收敛。 在检测到判定反馈均衡器抽头收敛之后，该方法基于第二抽头量化调整施加到抽头系数的校正电压，其中第二抽头量化与第一抽头量化不同。

公开(公告)号：US08816776B2

公开(公告)日：2014-08-26

申请号：US13675520

申请日：2012-11-13

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/085 ,  H04L7/033 ,  H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。

公开(公告)号：US09197460B1

公开(公告)日：2015-11-24

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。

公开(公告)号：US08923371B2

公开(公告)日：2014-12-30

申请号：US13729405

申请日：2012-12-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/38 ,  H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US08848769B2

公开(公告)日：2014-09-30

申请号：US13647502

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Mohammad Mobin ,  Vladimir Sindalovsky ,  Amaresh Malipatil ,  Thomas F. Gibbons, Jr. ,  Ye Liu ,  Lane A. Smith

IPC: H04B1/38 ,  H04L5/16 ,  H04B1/40

CPC classification number: H04B1/40 ,  H04L25/03343 ,  H04L25/03885

Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.

Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。

公开(公告)号：US08803573B2

公开(公告)日：2014-08-12

申请号：US13647470

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Joseph Anidjar ,  Lane A. Smith ,  Brett David Hardy

IPC: H03L7/06

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/1075 ,  H03L7/146 ,  H03L2207/06

Abstract: In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Abstract translation: 在所描述的实施例中，用于SerDes设备的基于VCO的CDR包括相位检测器，响应于第一控制信号的VCO和第二控制信号，并产生输出信号;频率校准模块，被配置为通过以下步骤校准输出信号的频率 执行粗略校准和随后的精细校准，齿轮控制模块及时控制第一和第二控制信号的增益变化，以及通过由频率校准模块产生的精细校准值产生的查找表，其中编程 通过采用存储在查表中的精细校准值的计算电路来计算变速控制模块的可变增益，计算电路的计算调节换档增益，并且调整换档增益，并且调整总体CDR 增益超过VCO控制曲线。

公开(公告)号：US20140185658A1

公开(公告)日：2014-07-03

申请号：US13729405

申请日：2012-12-28

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US20140098844A1

公开(公告)日：2014-04-10

申请号：US13647502

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Mohammad Mobin ,  Vladimir Sindalovsky ,  Amaresh Malipatil ,  Thomas F. Gibbons, JR. ,  Ye Liu ,  Lane A. Smith

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L25/03343 ,  H04L25/03885

Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.

Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。