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公开(公告)号:US11948895B2
公开(公告)日:2024-04-02
申请号:US17810625
申请日:2022-07-04
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung Lin , Chia-Cheng Chang , I-Hsuan Peng , Nai-Wei Liu
IPC: H01L23/00 , H01L23/043 , H01L23/13 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L23/562 , H01L23/043 , H01L23/13 , H01L23/3135 , H01L23/49816 , H01L23/49838 , H01L23/5383 , H01L24/16 , H01L25/0655 , H01L23/5385 , H01L2224/16227
Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.
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公开(公告)号:US11791266B2
公开(公告)日:2023-10-17
申请号:US17886704
申请日:2022-08-12
Applicant: MediaTek Inc.
Inventor: Yen-Yao Chi , Nai-Wei Liu , Ta-Jen Yu , Tzu-Hung Lin , Wen-Sung Hsu
CPC classification number: H01L23/5283 , H01L21/561 , H01L21/563 , H01L21/565 , H01L23/293 , H01L23/3114 , H01L23/3121 , H01L23/3171 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/96 , H01L2224/0231 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401
Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
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公开(公告)号:US20230073399A1
公开(公告)日:2023-03-09
申请号:US17989498
申请日:2022-11-17
Applicant: MediaTek Inc.
Inventor: Yen-Yao Chi , Nai-Wei Liu , Ta-Jen Yu , Tzu-Hung Lin , Wen-Sung Hsu , Shih-Chin Lin
Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
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公开(公告)号:US11508678B2
公开(公告)日:2022-11-22
申请号:US16910354
申请日:2020-06-24
Applicant: MEDIATEK INC.
Inventor: Yen-Yao Chi , Nai-Wei Liu , Tzu-Hung Lin
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an antenna device and semiconductor package. The antenna device includes a conductive pattern layer including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate. The antenna device also includes a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The semiconductor package includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer. The semiconductor package also includes a first semiconductor die electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first semiconductor die.
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公开(公告)号:US10217723B2
公开(公告)日:2019-02-26
申请号:US15644849
申请日:2017-07-10
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung Lin , I-Hsuan Peng , Nai-Wei Liu , Wei-Che Huang
IPC: H01L23/00 , H01L25/00 , H01L25/065 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/538 , H01L29/06
Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
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公开(公告)号:US09941260B2
公开(公告)日:2018-04-10
申请号:US15203418
申请日:2016-07-06
Applicant: MediaTek Inc.
Inventor: Tzu-Hung Lin , Chi-Chin Lien , Nai-Wei Liu , I-Hsuan Peng , Ching-Wen Hsiao , Wei-Che Huang
IPC: H01L23/00 , H01L25/10 , H01L25/00 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/49833 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
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公开(公告)号:US11742564B2
公开(公告)日:2023-08-29
申请号:US17321914
申请日:2021-05-17
Applicant: MediaTek Inc.
Inventor: Nai-Wei Liu , Yen-Yao Chi , Tzu-Hung Lin , Wen-Sung Hsu
CPC classification number: H01Q1/2283 , H01L23/3128 , H01L23/3135 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L23/66 , H01L24/20 , H01Q1/38 , H01Q9/16 , H01L2223/6677 , H01L2224/211 , H01L2224/221
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.
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公开(公告)号:US10957611B2
公开(公告)日:2021-03-23
申请号:US16002138
申请日:2018-06-07
Applicant: MEDIATEK INC.
Inventor: Chia-Cheng Chang , Tzu-Hung Lin , I-Hsuan Peng , Nai-Wei Liu
IPC: H01L23/053 , H01L23/16 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/16 , H01L23/00 , H01L25/065 , H01L23/04 , H01L25/18 , H01L23/433 , H01L23/373
Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
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公开(公告)号:US10692789B2
公开(公告)日:2020-06-23
申请号:US15968449
申请日:2018-05-01
Applicant: MediaTek Inc.
Inventor: Nai-Wei Liu , Tzu-Hung Lin , I-Hsuan Peng , Ching-Wen Hsiao , Wei-Che Huang
IPC: H01L23/31 , H01L23/538 , H01L23/00 , H01L23/498 , H01L21/56
Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
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公开(公告)号:US20200013735A1
公开(公告)日:2020-01-09
申请号:US16452395
申请日:2019-06-25
Applicant: MediaTek Inc.
Inventor: Nai-Wei Liu , Yen-Yao Chi , Yeh-Chun Kao , Shih-Huang Yeh , Tzu-Hung Lin , Wen-Sung Hsu
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective.
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