公开(公告)号：US20250006236A1

公开(公告)日：2025-01-02

申请号：US18882436

申请日：2024-09-11

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Alan J. Wilson ,  Donald Martin Morgan

IPC: G11C7/24 ,  G11C7/10 ,  G11C8/20

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

公开(公告)号：US12118211B2

公开(公告)日：2024-10-15

申请号：US18100803

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

公开(公告)号：US12112831B2

公开(公告)日：2024-10-08

申请号：US17877592

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Alan J. Wilson ,  Donald Martin Morgan

IPC: G11C8/20 ,  G11C7/10 ,  G11C7/24

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/1066 ,  G11C8/20

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

公开(公告)号：US20230350580A1

公开(公告)日：2023-11-02

申请号：US17730755

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

公开(公告)号：US11804281B2

公开(公告)日：2023-10-31

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/16 ,  G06F11/18

CPC classification number: G11C29/70 ,  G06F11/16 ,  G06F11/1666 ,  G06F11/18

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

公开(公告)号：US11579772B2

公开(公告)日：2023-02-14

申请号：US17105000

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

公开(公告)号：US20210263848A1

公开(公告)日：2021-08-26

申请号：US16796860

申请日：2020-02-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Alan J. Wilson

IPC: G06F12/06

Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.

公开(公告)号：US20210020261A1

公开(公告)日：2021-01-21

申请号：US17062264

申请日：2020-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Alan J. Wilson

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/32 ,  G11C17/18 ,  G11C11/408 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

公开(公告)号：US20180005710A1

公开(公告)日：2018-01-04

申请号：US15703223

申请日：2017-09-13

Applicant: Micron Technology, Inc.

Inventor： Alan J. Wilson ,  Jeffrey Wright

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/408 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C7/24 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/70 ,  G11C29/789 ,  G11C29/806 ,  G11C29/838 ,  G11C2029/4402

Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

公开(公告)号：US09741403B2

公开(公告)日：2017-08-22

申请号：US14539331

申请日：2014-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Alan J. Wilson ,  Jeffrey P. Wright

IPC: G11C5/00 ,  G11C7/20 ,  G11C11/4072 ,  G11C16/20 ,  G11C29/02 ,  G11C11/4093 ,  G11C11/4076 ,  G11C16/06 ,  G11C7/22 ,  G11C17/18

CPC classification number: G11C7/20 ,  G11C5/063 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/06 ,  G11C16/20 ,  G11C17/18 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/14 ,  G11C29/46 ,  G11C29/70

Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.