公开(公告)号：US12200929B2

公开(公告)日：2025-01-14

申请号：US17408813

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  M. Jared Barclay ,  Bhavesh Bhartia ,  Chet E. Carter ,  John D. Hopkins ,  Andrew Li ,  Haoyu Li ,  Alyssa N. Scarbrough ,  Grady S. Waldo

IPC: H01L27/11582 ,  H10B41/27 ,  H10B43/27

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

公开(公告)号：US20240244840A1

公开(公告)日：2024-07-18

申请号：US18620002

申请日：2024-03-28

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H10B43/10 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/3215 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/10 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32155 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US11974429B2

公开(公告)日：2024-04-30

申请号：US17091238

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H10B43/10 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/3215 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/10 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32155 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20230207458A1

公开(公告)日：2023-06-29

申请号：US18046111

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  Jay S. Brown ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Rita J. Klein

IPC: H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.

公开(公告)号：US20230207010A1

公开(公告)日：2023-06-29

申请号：US17583472

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  M. Jared Barclay ,  John D. Hopkins

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20230021060A1

公开(公告)日：2023-01-19

申请号：US17377949

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Alyssa N. Scarbrough

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230011135A1

公开(公告)日：2023-01-12

申请号：US17368395

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/423

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220328349A1

公开(公告)日：2022-10-13

申请号：US17227734

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shuangqiang Luo ,  Alyssa N. Scarbrough

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.

公开(公告)号：US20220319985A1

公开(公告)日：2022-10-06

申请号：US17844565

申请日：2022-06-20

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11582

Abstract: Some embodiments include a method in which a first stack of alternating first and second levels is formed. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels and one of the first levels. An etch-stop material and a liner are formed over the stack. A first material is formed over the etch-stop material. Openings are formed to extend through the first material to the etch-stop material. Sacrificial material is formed within the openings. A second stack is formed over the first stack. A second material is formed over the first material. Conductive layers are formed within the first levels. Additional openings are formed to extend to the sacrificial material, and are then extended through the sacrificial material to the conductive layers within the steps. Some embodiments include integrated assemblies.