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    WRITE LEVEL INITIALIZATION SYNCRONIZATION
    2.
    发明申请
    WRITE LEVEL INITIALIZATION SYNCRONIZATION 审中-公开

    公开(公告)号：US20190235760A1

    公开(公告)日：2019-08-01

    申请号：US15883956

    申请日：2018-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

    IPC: G06F3/06

    Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

    Distributed mode registers in memory devices
    3.
    发明授权
    Distributed mode registers in memory devices 有权

    公开(公告)号：US10068648B1

    公开(公告)日：2018-09-04

    申请号：US15691217

    申请日：2017-08-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Thanh K. Mai ,  Gary Howe

    IPC: G11C7/00 ,  G11C16/08 ,  G11C11/406 ,  G11C11/16

    Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

    COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION
    4.
    发明申请
    COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION 审中-公开

    公开(公告)号：US20190065106A1

    公开(公告)日：2019-02-28

    申请号：US15691447

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Gary Howe

    IPC: G06F3/06 ,  G11C11/408

    Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

    APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING
    9.
    发明申请
    APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING 审中-公开

    公开(公告)号：US20170357482A1

    公开(公告)日：2017-12-14

    申请号：US15690085

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Brian Huber ,  Gary Howe

    IPC: G06F5/06 ,  H03K5/26

    CPC classification number: G06F5/06 ,  H03K5/26

    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

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