公开(公告)号：US11805638B2

公开(公告)日：2023-10-31

申请号：US17202144

申请日：2021-03-15

申请人： Micron Technology, Inc.

发明人： Seiji Narui ,  Yuki Ebihara

IPC分类号： G11C19/08 ,  H10B12/00 ,  G11C11/4074 ,  G11C19/28 ,  G06F5/06

CPC分类号： H10B12/315 ,  G06F5/06 ,  G11C11/4074 ,  G11C19/0875 ,  G11C19/287

摘要： Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US20230215828A1

公开(公告)日：2023-07-06

申请号：US17823638

申请日：2022-08-31

申请人： Micron Technology, Inc.

发明人： Andreas Kuesel ,  Takamasa Suzuki ,  Jens Polney ,  Seiji Narui ,  Shiro Uchiyama

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/09 ,  H01L25/0657 ,  H01L24/16 ,  H01L25/50 ,  H01L24/08 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/09179 ,  H01L2224/09133 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2224/16145 ,  H01L2224/09515 ,  H01L2224/09153 ,  H01L2224/08056 ,  H01L2924/30105 ,  H01L2225/06593 ,  H01L2225/06544

摘要： Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.

公开(公告)号：US20230215494A1

公开(公告)日：2023-07-06

申请号：US17565951

申请日：2021-12-30

申请人： MICRON TECHNOLOGY, INC.

发明人： Tomohiko Yamagishi ,  Seiji Narui ,  Kiyoshi Nakai ,  Takamasa Suzuki

IPC分类号： G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C29/42

CPC分类号： G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C29/42

摘要： Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.

公开(公告)号：US11244888B2

公开(公告)日：2022-02-08

申请号：US17164454

申请日：2021-02-01

申请人： MICRON TECHNOLOGY, INC.

发明人： Naohisa Nishioka ,  Seiji Narui

IPC分类号： H01L23/00 ,  H01L23/48 ,  G11C29/44 ,  G11C7/10 ,  G11C5/06

摘要： Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

公开(公告)号：US20210183744A1

公开(公告)日：2021-06-17

申请号：US17164454

申请日：2021-02-01

申请人： MICRON TECHNOLOGY, INC.

发明人： Naohisa Nishioka ,  Seiji Narui

IPC分类号： H01L23/48 ,  G11C29/44 ,  G11C7/10 ,  G11C5/06

摘要： Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

公开(公告)号：US10916489B1

公开(公告)日：2021-02-09

申请号：US16590760

申请日：2019-10-02

申请人： MICRON TECHNOLOGY, INC.

发明人： Naohisa Nishioka ,  Seiji Narui

IPC分类号： G11C5/06 ,  H01L23/48 ,  G11C29/44 ,  G11C7/10

摘要： Disclosed herein is an apparatus that includes a memory cell army, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

公开(公告)号：US10664432B2

公开(公告)日：2020-05-26

申请号：US15987895

申请日：2018-05-23

申请人： Micron Technology, Inc.

发明人： Yuki Ebihara ,  Seiji Narui

IPC分类号： G11C11/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

摘要： Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US10163469B2

公开(公告)日：2018-12-25

申请号：US15365563

申请日：2016-11-30

申请人： Micron Technology, Inc.

发明人： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC分类号： G11C7/10 ,  G11C19/28 ,  G11C7/22

摘要： Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US11264068B2

公开(公告)日：2022-03-01

申请号：US17122801

申请日：2020-12-15

申请人： MICRON TECHNOLOGY, INC.

发明人： Ryosuke Yatsushiro ,  Seiji Narui

IPC分类号： G11C5/06 ,  G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  H01L25/065 ,  H01L25/18

摘要： Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.

公开(公告)号：US11004475B2

公开(公告)日：2021-05-11

申请号：US15938819

申请日：2018-03-28

申请人： MICRON TECHNOLOGY, INC.

发明人： Seiji Narui

IPC分类号： G11C5/02 ,  H01L25/065 ,  G11C5/04 ,  H01L27/105

摘要： Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.