公开(公告)号：US09721668B2

公开(公告)日：2017-08-01

申请号：US14820209

申请日：2015-08-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Kuo-Pin Chang

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L27/24

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/24

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

公开(公告)号：US09373409B2

公开(公告)日：2016-06-21

申请号：US14326212

申请日：2014-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Chih-Shen Chang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5622 ,  G11C2211/5648

Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.

Abstract translation: 编程具有交替页面取向的3D NAND闪存的常见问题包括背景图案效果和图案引起的程序干扰。 改进的编程技术可以显着地减少这些问题，并且在设置存储器单元的阈值电压时又提高精度。 提供了组合“逐字线”编程和“逐页”编程的方面的示例性技术。 这样，每个页面可以从最接近字符串选择结构的存储器单元开始编程，并且可以基本上同时编程多个偶数页或奇数页上的存储器单元。

公开(公告)号：US09361989B1

公开(公告)日：2016-06-07

申请号：US14571351

申请日：2014-12-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/24

Abstract: A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word lines, and the second memory string is coupled to a second bit line and the word lines. When an erasing voltage is applied to the word lines, a first voltage is applied to the first bit line to erase data stored in the first memory string, and a second voltage is applied to the second bit line to set the second memory string to be floating.

Abstract translation: 存储器件包括第一存储器串和第二存储器串。 第一存储器串耦合到第一位线和多个字线，并且第二存储器串耦合到第二位线和字线。 当擦除电压施加到字线时，第一电压被施加到第一位线以擦除存储在第一存储器串中的数据，并且第二电压被施加到第二位线，以将第二存储器串设置为 浮动

公开(公告)号：US20140211563A1

公开(公告)日：2014-07-31

申请号：US13940010

申请日：2013-07-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang ,  Wen-Wei Yeh ,  Chih-Shen Chang ,  Hang-Ting Lue

IPC: G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3427

Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。

公开(公告)号：US08760928B2

公开(公告)日：2014-06-24

申请号：US13710992

申请日：2012-12-11

Applicant: Macronix International Co., Ltd

Inventor： Ti-Wen Chen ,  Hang-Ting Lue ,  Shuo-Nan Hung ,  Shih-Lin Huang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。

公开(公告)号：US09761319B1

公开(公告)日：2017-09-12

申请号：US15344614

申请日：2016-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445

Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

公开(公告)号：US09607702B2

公开(公告)日：2017-03-28

申请号：US14668728

申请日：2015-03-25

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483

Abstract: A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of word lines between the first and second string select switches. A channel-side voltage can be applied to the channel lines. A control voltage can be applied to a selected subset of the first string select switches. The channel lines can be floated at ends of the second string select switches. Tunneling in memory cells coupled to an unselected subset of the first string select switches can be inhibited. Word line-side erase voltages can be applied to word lines in the set of word lines in the block to induce tunneling in memory cells coupled to the word lines and coupled to the selected subset of the first string select switches.

公开(公告)号：US20160172040A1

公开(公告)日：2016-06-16

申请号：US14571351

申请日：2014-12-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/24

Abstract: A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word lines, and the second memory string is coupled to a second bit line and the word lines. When an erasing voltage is applied to the word lines, a first voltage is applied to the first bit line to erase data stored in the first memory string, and a second voltage is applied to the second bit line to set the second memory string to be floating.

Abstract translation: 存储器件包括第一存储器串和第二存储器串。 第一存储器串耦合到第一位线和多个字线，并且第二存储器串耦合到第二位线和字线。 当擦除电压施加到字线时，第一电压被施加到第一位线以擦除存储在第一存储器串中的数据，并且第二电压被施加到第二位线，以将第二存储器串设置为 浮动

公开(公告)号：US09177662B1

公开(公告)日：2015-11-03

申请号：US14481953

申请日：2014-09-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wen-Wei Yeh ,  Chih-Shen Chang ,  Kuo-Pin Chang

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10

Abstract: A pre-reading method and a programming method for a 3D NAND flash memory are provided. The pre-reading method comprises the following steps. A selected string includes a first memory cell, two second memory cells and a plurality of third memory cells. The two second memory cells are adjacent to the first memory cell. The third memory cells are not adjacent to the first memory cell. A first pass voltage is applied on the second memory cells, a second pass voltage is applied on the third memory cells, and a read voltage is applied on the first memory cell via a plurality of word lines for reading a data of the first memory cell. The first pass voltage is larger than the second pass voltage.

Abstract translation: 提供了一种用于3D NAND闪存的预读方法和编程方法。 预读方法包括以下步骤。 所选择的串包括第一存储器单元，两个第二存储器单元和多个第三存储器单元。 两个第二存储单元与第一存储单元相邻。 第三存储单元不与第一存储单元相邻。 对第二存储单元施加第一通过电压，在第三存储单元施加第二通过电压，并且经由用于读取第一存储单元的数据的多条字线将读取电压施加在第一存储单元上 。 第一通过电压大于第二通过电压。

公开(公告)号：US10886222B2

公开(公告)日：2021-01-05

申请号：US16380040

申请日：2019-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei Jiang ,  Kuo-Pin Chang ,  Chih-Wei Hu

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/11568 ,  H01L21/311 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/321

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.