摘要:
An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要:
A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.
摘要:
A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.
摘要:
A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
摘要:
Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.
摘要:
A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.
摘要:
A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要:
A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.
摘要:
A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要:
In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.