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    FEEDBACK CALIBRATION OF DIGITAL TO TIME CONVERTER
    2.
    发明申请
    FEEDBACK CALIBRATION OF DIGITAL TO TIME CONVERTER 有权
    数字到时间转换器的反馈校准

    公开(公告)号：US20150188583A1

    公开(公告)日：2015-07-02

    申请号：US14140801

    申请日：2013-12-26

    申请人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

    发明人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

    IPC分类号： H04B1/04 ,  H03M1/84

    CPC分类号： H04B17/21 ,  H03F1/3241 ,  H03M1/1009 ,  H03M1/82 ,  H03M1/84 ,  H04B1/0475 ,  H04B2001/0425

    摘要： This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.

    摘要翻译： 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。

    Digital Voltage Ramp Generator
    3.
    发明申请
    Digital Voltage Ramp Generator 审中-公开
    数字电压斜坡发生器

    公开(公告)号：US20150116012A1

    公开(公告)日：2015-04-30

    申请号：US14066961

    申请日：2013-10-30

    申请人： Hasnain Lakdawala ,  Eshel Gordon ,  Ofir Degani ,  Ashoke Ravi ,  Thomas W. Brown

    发明人： Hasnain Lakdawala ,  Eshel Gordon ,  Ofir Degani ,  Ashoke Ravi ,  Thomas W. Brown

    IPC分类号： H03K4/12

    CPC分类号： H03K4/12 ,  H03K4/48 ,  H03K4/502

    摘要： According to some embodiments, an all digital ramp generator may use a string of series connected delays or digital to time-based circuits to perform voltage ramp generation. Thus in some embodiments conventional operational amplifier circuits and relaxation oscillators may be replaced for generating triangular ramp waveforms for DC to DC or direct time-based DC to DC converters. The use of delay lines may produce sufficient resolution for many applications. Thus time domain techniques may afford a more digital approach that scales with process technology and allows high speed operation in some embodiments. A design based on use of inverters and capacitors may scale well with process technology. The decoder and drive logic may be integrated into the voltage ramp generation in some embodiments.

    摘要翻译： 根据一些实施例，全数字斜坡发生器可以使用串联连接的延迟串或数字到基于时间的电路来执行电压斜坡生成。 因此，在一些实施例中，常规运算放大器电路和弛豫振荡器可以被替换以产生用于直流到直流或直接基于时间的直流到直流转换器的三角形斜坡波形。 使用延迟线可以为许多应用产生足够的分辨率。 因此，时域技术可以提供与数字处理技术相比较的数字化方法，并且在一些实施例中允许高速操作。 基于逆变器和电容器的设计可以与工艺技术相结合。 在一些实施例中，解码器和驱动逻辑可以集成到电压斜坡生成中。

    Transmitter control
    5.
    发明授权
    Transmitter control 有权
    变送器控制

    公开(公告)号：US07653147B2

    公开(公告)日：2010-01-26

    申请号：US11206447

    申请日：2005-08-17

    申请人： Georgios Palaskas ,  Stewart S. Taylor ,  Hasnain Lakdawala

    发明人： Georgios Palaskas ,  Stewart S. Taylor ,  Hasnain Lakdawala

    IPC分类号： H04L25/03

    CPC分类号： H03G3/3042 ,  H03F1/0205 ,  H03F1/0261 ,  H03F1/3241 ,  H03F1/3294 ,  H03F3/24 ,  H03F2200/336 ,  H03F2200/393 ,  H04L27/367 ,  H04L27/368

    摘要： An apparatus for transmitter control is disclosed. The apparatus includes an analog circuit designed to operate on at least a portion of a communications signal to be wirelessly transmitted, based at least in part on a control signal. The apparatus includes a lookup table coupled to the analog circuit, with the lookup table designed to output the control signal based at least in part on the communications signal, or one or more measured metrics of the communications signal. Embodiments of the present invention include, but are not limited to, methods encompassing the operations described above, as well as subsystems and systems designed to operate in the above described manner.

    摘要翻译： 公开了一种用于发射机控制的装置。 该装置包括至少部分地基于控制信号而被设计为对要进行无线传输的通信信号的至少一部分进行操作的模拟电路。 该装置包括耦合到模拟电路的查找表，其中查找表被设计为至少部分地基于通信信号或通信信号的一个或多个测量的度量来输出控制信号。 本发明的实施例包括但不限于包括上述操作的方法以及被设计为以上述方式操作的子系统和系统。

    Stochastic beating time-to-digital converter (TDC)
    7.
    发明授权
    Stochastic beating time-to-digital converter (TDC) 失效
    随机抖动时间 - 数字转换器（TDC）

    公开(公告)号：US08773182B1

    公开(公告)日：2014-07-08

    申请号：US13756670

    申请日：2013-02-01

    申请人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala ,  Rotem Banin

    发明人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala ,  Rotem Banin

    IPC分类号： H03L7/06

    CPC分类号： H03L7/085 ,  G04F10/005 ,  H03L2207/50

    摘要： A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.

    摘要翻译： 随机抖动时间 - 数字转换器（TDC）可以包括触发环形振荡器（TRO）和随机TDC（sTDC）。 当由参考信号沿触发时，TRO可以产生具有作为压控振荡器（VCO）周期的选定比率的TRO周期的周期性TRO信号。 TRO周期可以大于或小于VCO周期的指定比率。 具有事件触发的存储器的sTDC可以包括具有多组锁存器的sTDC组件。 每组锁存器可以配置为在TRO信号的边沿采样和存储VCO状态。 当锁存器组中的一个锁存器转变为被称为过渡沿的不同数字状态时，sTDC组件可以触发锁存器组的选定数量的VCO状态的捕获。

    RESISTOR-BASED SIGMA-DELTA DAC
    8.
    发明申请
    RESISTOR-BASED SIGMA-DELTA DAC 有权
    基于电阻的SIGMA-DELTA DAC

    公开(公告)号：US20130271305A1

    公开(公告)日：2013-10-17

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/78

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    SIGMA-DELTA CONVERTER NOISE CANCELLATION
    9.
    发明申请
    SIGMA-DELTA CONVERTER NOISE CANCELLATION 有权
    SIGMA-DELTA转换器噪声消除

    公开(公告)号：US20100079324A1

    公开(公告)日：2010-04-01

    申请号：US12239294

    申请日：2008-09-26

    申请人： Hasnain Lakdawala ,  Soumyanath Krishnamurthy

    发明人： Hasnain Lakdawala ,  Soumyanath Krishnamurthy

    IPC分类号： H03M3/00

    CPC分类号： H03M3/344 ,  H03M3/46

    摘要： Embodiments provide apparatuses, systems, and methods to convert an analog signal input into a sigma-delta digital output at a high sampling rate and correct for noise components of the digital output. An analog filter coupled to a sigma-delta converter accepts a noise-shaped analog signal from the sigma-delta converter to attenuate signal components of the noise-shaped analog signal at a plurality of folding frequencies associated with a sampling rate of a low-speed Analog-To-Digital (ADC) to produce a filtered output. The low-speed ADC is coupled to an output of the analog filter and samples the filtered output of the analog filter at a sampling rate slower than the high sample rate to output an ADC digital output. Other embodiments may be described and claimed.

    摘要翻译： 实施例提供了以高采样率将模拟信号输入转换成Σ-Δ数字输出并校正数字输出的噪声分量的装置，系统和方法。 耦合到Σ-Δ转换器的模拟滤波器接收来自Σ-Δ转换器的噪声形模拟信号，以与低速采样率相关联的多个折叠频率衰减噪声形模拟信号的信号分量 模数转换（ADC）产生滤波输出。 低速ADC耦合到模拟滤波器的输出，并以低于采样率的采样速率对模拟滤波器的滤波后的输出采样，以输出ADC数字输出。 可以描述和要求保护其他实施例。

    DUAL DATA WEIGHTED AVERAGE DYNAMIC ELEMENT MATCHING IN ANALOG-TO-DIGITAL
    10.
    发明申请
    DUAL DATA WEIGHTED AVERAGE DYNAMIC ELEMENT MATCHING IN ANALOG-TO-DIGITAL 有权
    双数据加权平均动态元素匹配模拟数字

    公开(公告)号：US20100052960A1

    公开(公告)日：2010-03-04

    申请号：US12203679

    申请日：2008-09-03

    申请人： Hasnain Lakdawala ,  Pukar Malla

    发明人： Hasnain Lakdawala ,  Pukar Malla

    IPC分类号： H03M3/00

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464

    摘要： Methods and systems to provide dynamic element matching (DEM) in multi-phase sample systems include multiple uncorrelated, dual data weighted averaging, dynamic element matching (DDWA DEM). DDWA DEM may be implemented in a multiple-phase sample system in which sample paths and feedback paths share capacitances. Compensation feedback is apportioned amongst corresponding banks of capacitive sample circuits to utilize the capacitive sample circuits within each bank substantially equally over multiple sample cycles. The apportioning is substantially un-correlated between banks, which may reduce in-band quantization noise folding. DDWA DEM may be implemented within a digital-to-analog converter (DAC), in a delta-sigma modulator.

    摘要翻译： 在多相样本系统中提供动态元素匹配（DEM）的方法和系统包括多个不相关的双重数据加权平均，动态元素匹配（DDWA DEM）。 DDWA DEM可以在采样路径和反馈路径共享电容的多相采样系统中实现。 补偿反馈在相应的电容采样电路组中分配，以在多个采样周期内基本上均等地利用每个存储体中的电容性采样电路。 分配在银行之间基本上是不相关的，这可能减少带内量化噪声折叠。 DDWA DEM可以在Δ-Σ调制器中的数模转换器（DAC）内实现。