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    SYSTEMS AND METHODS FOR CONTROLLING DC-DC CONVERTERS USING PARTIAL RESETS
    1.
    发明申请
    SYSTEMS AND METHODS FOR CONTROLLING DC-DC CONVERTERS USING PARTIAL RESETS 审中-公开

    公开(公告)号：US20190229620A1

    公开(公告)日：2019-07-25

    申请号：US16100070

    申请日：2018-08-09

    Applicant: MediaTek Inc.

    Inventor： Yueh-Min Chen ,  Yu-Hsin Lin

    IPC: H02M3/158 ,  H02M1/08 ,  H02M3/07

    Abstract: Direct current-direct current (DC-DC) converters including buck converters are described. These DC-DC converters may be configured to reduce oscillations that would otherwise arise in the output reference voltage due to ringing effects without significantly lengthening the duration of the transient period. These DC converters may leverage a feedback voltage generated by sensing the current flowing through the inductor of the buck converter. The feedback voltage may compared to a threshold, and the signal resulting from the comparison may be used to vary the reference voltage. The DC-DC converter may be operated in a “partial reset mode,” in which the voltage generated by sensing the inductor's current is reduced to a value greater than zero in response to the feedback voltage reaching the threshold. Reducing the sense voltage in this manner may reduce the duration of the transient period.

    LOW-RIPPLE LATCH CIRCUIT FOR REDUCING SHORT-CIRCUIT CURRENT EFFECT
    4.
    发明申请
    LOW-RIPPLE LATCH CIRCUIT FOR REDUCING SHORT-CIRCUIT CURRENT EFFECT 有权
    用于减少短路电流效应的低纹波锁存电路

    公开(公告)号：US20160336927A1

    公开(公告)日：2016-11-17

    申请号：US15044114

    申请日：2016-02-16

    Applicant: MEDIATEK INC.

    Inventor： Chen-Yen Ho ,  Yu-Hsin Lin

    IPC: H03K3/356 ,  H03M1/66

    CPC classification number: H03K3/356113 ,  H03K3/356121 ,  H03K3/356191 ,  H03M1/066 ,  H03M1/0872 ,  H03M1/66 ,  H03M3/464

    Abstract: A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

    Abstract translation: 锁存电路包括输入级，放大级和时钟门控电路。 输入级被布置成用于接收至少一个时钟信号和数据控制信号。 放大级与输入级耦合，由供电电压和接地电压提供，并被配置为保持数据值并根据时钟信号和数据控制信号输出数据值。 时钟门控电路耦合到放大级，并且被布置为避免电源电压和接地电压之间的短路电流。

    UE ASSISTED INFORMATION FOR DUAL ACCESS/STEER FEATURE
    5.
    发明申请
    UE ASSISTED INFORMATION FOR DUAL ACCESS/STEER FEATURE 有权

    公开(公告)号：US20250088954A1

    公开(公告)日：2025-03-13

    申请号：US18826606

    申请日：2024-09-06

    Applicant: MEDIATEK INC.

    Inventor： Chia-Lin Lai ,  Tze Jie Tan ,  Yuan-Chieh Lin ,  Yu-Hsin Lin

    IPC: H04W48/18

    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The method may be performed by a mobile device. In certain configurations, the mobile device registers a first network access of a first public land mobile network (PLMN). After registering to the first network access, the mobile device determines, based on first information, whether a second network access of a PLMN or a Standalone Non-Public Network (SNPN) is allowed for the UE to register thereto. In response to determining the second network access is allowed, the mobile device selects the second network access based on the first information, and registers to the second network access. The second network access may be a network access of the first PLMN, or may be a network access of a second different PLMN or the SNPN.

    DEREGISTRATION AND EMM PARAMETER HANDLING CONSIDERING ACCESS TYPE
    6.
    发明公开
    DEREGISTRATION AND EMM PARAMETER HANDLING CONSIDERING ACCESS TYPE 审中-公开

    公开(公告)号：US20240155535A1

    公开(公告)日：2024-05-09

    申请号：US18493756

    申请日：2023-10-24

    Applicant: MEDIATEK INC.

    Inventor： Yu-Hsin Lin ,  YUAN-CHIEH LIN

    IPC: H04W60/06

    CPC classification number: H04W60/06

    Abstract: A method of handling de-registration and EPS mobility management (EMM) parameter for 3GPP when UE receives a de-registration request message via non-3GPP is proposed. There is an access type in the de-registration type IE in the de-registration request message. In one novel aspect, a UE handles EMM parameters of the de-registration procedure depending on the received access type in the de-registration type IE. Upon receiving a DEREGISTRATION REQUEST message, if the de-registration request is for 3GPP access or for 3GPP access and non-3GPP access, the UE performs a local release of the PDU sessions over 3GPP access and non-3GPP access, if any. Based on the 5GMM cause, UE also handles the corresponding EMM parameters including EMM state, EPS update status, 4G-GUTI, last visited registered TAI, TAI list, eKSI and attach attempt counter.

    LOW POWER QUADRATURE PHASE DETECTOR
    7.
    发明申请
    LOW POWER QUADRATURE PHASE DETECTOR 有权

    公开(公告)号：US20230113143A1

    公开(公告)日：2023-04-13

    申请号：US17857161

    申请日：2022-07-04

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03L7/087 ,  H03L7/107 ,  H03L7/07 ,  H03K17/687

    Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

    FILTER CIRCUIT USING POLYPHASE FILTER WITH DYNAMIC RANGE ENHANCEMENT
    8.
    发明申请
    FILTER CIRCUIT USING POLYPHASE FILTER WITH DYNAMIC RANGE ENHANCEMENT 有权

    公开(公告)号：US20220182040A1

    公开(公告)日：2022-06-09

    申请号：US17503385

    申请日：2021-10-18

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03H11/04

    Abstract: A filter circuit includes a polyphase filter used to generate a plurality of output signals with different phases according to a plurality of input signals. The polyphase filter includes a switch circuit and a feed-forward capacitor. The switch circuit has a control terminal used to receive a control voltage, a first connection terminal used to output one of the output signals, and a second connection terminal used to receive one of the input signals. The feed-forward capacitor has a first plate coupled to the second connection terminal of the switch circuit and a second plate coupled to the control terminal of the switch circuit.

    LOW-NOISE DIFFERENTIAL TO SINGLE-ENDED CONVERTER
    10.
    发明申请
    LOW-NOISE DIFFERENTIAL TO SINGLE-ENDED CONVERTER 审中-公开

    公开(公告)号：US20200304083A1

    公开(公告)日：2020-09-24

    申请号：US16813630

    申请日：2020-03-09

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Yu-Hsin Lin

    IPC: H03F3/45

    Abstract: The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.

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