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    METHOD OF FORMING AN INTEGRATED CIRCUIT VIA
    2.
    发明申请
    METHOD OF FORMING AN INTEGRATED CIRCUIT VIA 有权

    公开(公告)号：US20230050344A1

    公开(公告)日：2023-02-16

    申请号：US17888057

    申请日：2022-08-15

    Applicant: Microchip Technology Incorporated

    Inventor： Daniel Baker ,  Justin Sato ,  Chris Sundahl

    IPC: H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L23/522

    Abstract: A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

    INTEGRATED INDUCTOR WITH A STACKED METAL WIRE
    3.
    发明公开
    INTEGRATED INDUCTOR WITH A STACKED METAL WIRE 审中-公开

    公开(公告)号：US20230268269A1

    公开(公告)日：2023-08-24

    申请号：US18140198

    申请日：2023-04-27

    Applicant: Microchip Technology Incorporated

    Inventor： Yaojian Leng ,  Justin Sato

    IPC: H01L23/522 ,  H01L23/532 ,  H01F27/32 ,  H01F27/28

    CPC classification number: H01L23/5227 ,  H01L23/53238 ,  H01L23/53223 ,  H01F27/32 ,  H01L28/10 ,  H01F27/2823 ,  H01L23/5329

    Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

    THREE-DIMENSIONAL METAL-INSULATOR-METAL (MIM) CAPACITOR
    4.
    发明申请
    THREE-DIMENSIONAL METAL-INSULATOR-METAL (MIM) CAPACITOR 有权

    公开(公告)号：US20220069069A1

    公开(公告)日：2022-03-03

    申请号：US17155431

    申请日：2021-01-22

    Applicant: Microchip Technology Incorporated

    Inventor： Yaojian Leng ,  Justin Sato

    IPC: H01L49/02 ,  H01L23/522

    Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

    BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER
    5.
    发明申请
    BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER 有权

    公开(公告)号：US20210335627A1

    公开(公告)日：2021-10-28

    申请号：US17111973

    申请日：2020-12-04

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Yaojian Leng ,  Bomy Chen ,  Chris Sundahl

    IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

    Abstract: Methods are provided for forming an integrated circuit (IC) package interposer configured for back-side attachment. A porous silicon double layer is formed on a bulk silicon wafer, e.g., using a controlled anodization, the porous silicon double layer including two porous silicon layers having different porosities. An interposer is formed over the porous silicon double layer, the interposer including back-side contacts, front-side contacts, and conductive structures (e.g., vias and metal interconnect) extending through the interposer to connect selected back-side contacts with selected front-side contacts. The structure is then split at the interface between the first and second porous silicon layers of the silicon double layer, and the interposer including the second porous silicon layers is inverted and etched to remove the second silicon layer and expose the back-side contacts, such that the exposed back-side contacts can be used for back-side attachment of the interposer to a package substrate or other structure.

    Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond
    6.
    发明授权
    Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond 有权

    公开(公告)号：US10896888B2

    公开(公告)日：2021-01-19

    申请号：US16157826

    申请日：2018-10-11

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

    IPC: H01L23/10 ,  H01L23/00 ,  H01L21/768

    Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

    INTEGRATED CIRCUIT (IC) DEVICE INCLUDING A FORCE MITIGATION SYSTEM FOR REDUCING UNDER-PAD DAMAGE CAUSED BY WIRE BOND
    7.
    发明申请
    INTEGRATED CIRCUIT (IC) DEVICE INCLUDING A FORCE MITIGATION SYSTEM FOR REDUCING UNDER-PAD DAMAGE CAUSED BY WIRE BOND 审中-公开

    公开(公告)号：US20190287936A1

    公开(公告)日：2019-09-19

    申请号：US16157826

    申请日：2018-10-11

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

    IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

    Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

    Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate
    9.
    发明授权
    Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate 有权

    公开(公告)号：US11723222B2

    公开(公告)日：2023-08-08

    申请号：US17074848

    申请日：2020-10-20

    Applicant: Microchip Technology Incorporated

    Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

    IPC: H10K19/00 ,  H10K19/10 ,  H01L49/02

    CPC classification number: H10K19/201 ,  H10K19/10 ,  H01L28/10

    Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

    Three-dimensional metal-insulator-metal (MIM) capacitor
    10.
    发明授权
    Three-dimensional metal-insulator-metal (MIM) capacitor 有权

    公开(公告)号：US11715757B2

    公开(公告)日：2023-08-01

    申请号：US18074617

    申请日：2022-12-05

    Applicant: Microchip Technology Incorporated

    Inventor： Yaojian Leng ,  Justin Sato

    IPC: H01L23/522 ,  H01L23/52 ,  H01L23/528 ,  H01L49/02

    CPC classification number: H01L28/91 ,  H01L23/5223

    Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

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