公开(公告)号：US08816509B2

公开(公告)日：2014-08-26

申请号：US13733481

申请日：2013-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Seok Hong ,  Kwang-chul Choi ,  Sangwon Kim ,  Hyun-Jung Song ,  Eun-Kyoung Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/29 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/29017 ,  H01L2224/29036 ,  H01L2224/29099 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/33051 ,  H01L2224/33505 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83986 ,  H01L2224/84201 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer.

Abstract translation: 半导体封装包括通过连接结构电互连的第一和第二半导体元件。 第一和第二半导体元件通过保护结构连接，保护结构包括由保持层包围的粘合剂层。

公开(公告)号：US09406592B2

公开(公告)日：2016-08-02

申请号：US14735300

申请日：2015-06-10

Applicant: Continental Automotive GmbH

Inventor： Nico Kohl ,  Martin Metzler ,  Sven Egelkraut ,  Markus Leicht

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49544 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49838 ,  H01L23/49844 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/29339 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/3756 ,  H01L2224/37639 ,  H01L2224/4001 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40221 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84201 ,  H01L2224/84203 ,  H01L2224/84205 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/84825 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/92142 ,  H01L2224/92246 ,  H01L2924/00015 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts.

Abstract translation: 功率半导体电路包括至少一个具有至少一个接触区域的半导体，以及至少一个接合导体条，其具有紧固在至少一个接触区域上的至少一个接触区域。 接合导体条的接触区域包括切口。

公开(公告)号：US20230154889A1

公开(公告)日：2023-05-18

申请号：US17954215

申请日：2022-09-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Manabu ISHIKAWA

IPC: H01L23/00 ,  H01L25/07 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L24/84 ,  H01L24/37 ,  H01L24/40 ,  H01L24/77 ,  H01L25/072 ,  H01L21/4882 ,  H01L23/3735 ,  H01L2224/37147 ,  H01L2224/37124 ,  H01L2224/84201 ,  H01L2224/77754 ,  H01L2224/7755 ,  H01L2224/40499 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29109 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2224/40225 ,  H01L2224/32225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2224/73221

Abstract: A semiconductor device manufacturing method, includes: a preparing process for preparing a conductive plate, a semiconductor chip arranged over the conductive plate with a first bonding material therebetween, and a connection terminal including a bonding portion arranged over the semiconductor chip with a second bonding material therebetween; a first jig arrangement process for arranging a first guide jig, through which a first guide hole pierces, over the conductive plate, such that the first guide hole corresponds to the bonding portion in a plan view of the semiconductor device; and a first pressing process for inserting a pillar-shaped pressing jig, which includes a pressing portion at a lower end portion thereof, into the first guide hole, and pressing the bonding portion of the connection terminal to a side of the conductive plate with the pressing portion.

公开(公告)号：US20130193588A1

公开(公告)日：2013-08-01

申请号：US13733481

申请日：2013-01-03

Applicant: Samsung Electronics Co, Ltd.

Inventor： Ji-Seok Hong ,  Kwang-chul Choi ,  Sangwon Kim ,  Hyun-Jung Song ,  Eun-Kyoung Choi

IPC: H01L23/29

CPC classification number: H01L23/29 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/29017 ,  H01L2224/29036 ,  H01L2224/29099 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/33051 ,  H01L2224/33505 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83986 ,  H01L2224/84201 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer.

Abstract translation: 半导体封装包括通过连接结构电互连的第一和第二半导体元件。 第一和第二半导体元件通过保护结构连接，保护结构包括由保持层包围的粘合剂层。

公开(公告)号：US20230290765A1

公开(公告)日：2023-09-14

申请号：US18064971

申请日：2022-12-13

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Julius Kovats ,  Anu Ramamurthy

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L25/0652 ,  H01L23/49811 ,  H01L24/40 ,  H01L24/16 ,  H01L24/73 ,  H01L24/48 ,  H01L24/37 ,  H01L24/84 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/37147 ,  H01L2224/40235 ,  H01L2224/48245 ,  H01L2224/73255 ,  H01L2224/40105 ,  H01L2224/40137 ,  H01L2224/40499 ,  H01L2924/0105 ,  H01L2224/84201 ,  H01L2224/95 ,  H01L2224/84007 ,  H01L23/49827 ,  H01L23/481

Abstract: An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.

公开(公告)号：US20170092574A1

公开(公告)日：2017-03-30

申请号：US15276623

申请日：2016-09-26

Applicant: Semikron Elektronik GmbH & Co., KG

Inventor： Florian WAGNER ,  Hartmut Kulas

IPC: H01L23/498 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/50 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3121 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/37599 ,  H01L2224/40221 ,  H01L2224/84201 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/0685 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/37099

Abstract: A method for producing a power-electronics switching device and a power electronic switching device produced thereby. In the power-electronics switching device, a power semiconductor component is arranged on a first region of a conductor track of a substrate. An insulating film comprising a cutout is then provided, wherein an overlap region of the insulating film, which overlap region is adjacent to the cutout, is designed to cover an edge region of the power semiconductor component. This is followed by arranging the insulating film on the substrate, with the power semiconductor component arranged on it, in such a way that the power semiconductor component is covered on all sides of its edge region by the covering region of the insulating film, wherein a further section of the insulating film covers parts of one of the conductor tracks. Finally, the connecting device is arranged.

公开(公告)号：US20150357303A1

公开(公告)日：2015-12-10

申请号：US14735300

申请日：2015-06-10

Applicant: Continental Automotive GmbH

Inventor： Nico Kohl ,  Martin Metzler ,  Sven Egelkraut ,  Markus Leicht

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49544 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49838 ,  H01L23/49844 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/29339 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/3756 ,  H01L2224/37639 ,  H01L2224/4001 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40221 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84201 ,  H01L2224/84203 ,  H01L2224/84205 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/84825 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/92142 ,  H01L2224/92246 ,  H01L2924/00015 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts.

Abstract translation: 功率半导体电路包括至少一个具有至少一个接触区域的半导体，以及至少一个接合导体条，其具有紧固在至少一个接触区域上的至少一个接触区域。 接合导体条的接触区域包括切口。